From 6b021de4a0f0400d21453d9913aba57c6b395f1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Tue, 28 Jan 2025 12:38:07 +0100 Subject: Add mecall backend --- rtic-macros/src/codegen/bindings/riscv_slic.rs | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'rtic-macros/src') diff --git a/rtic-macros/src/codegen/bindings/riscv_slic.rs b/rtic-macros/src/codegen/bindings/riscv_slic.rs index f2dc9ed..679ed8b 100644 --- a/rtic-macros/src/codegen/bindings/riscv_slic.rs +++ b/rtic-macros/src/codegen/bindings/riscv_slic.rs @@ -108,10 +108,6 @@ pub fn pre_init_checks(app: &App, _analysis: &SyntaxAnalysis) -> Vec Vec { let mut stmts = vec![]; - // First, we reset and disable all the interrupt controllers - stmts.push(quote!(rtic::export::clear_interrupts();)); - - // Then, we set the corresponding priorities let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id)); for (&p, name) in interrupt_ids.chain( app.hardware_tasks @@ -122,8 +118,7 @@ pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec< rtic::export::set_priority(slic::SoftwareInterrupt::#name, #p); )); } - // Finally, we activate the interrupts - stmts.push(quote!(rtic::export::set_interrupts();)); + stmts } -- cgit v1.2.3