From 1f6b6a42e5d581300dc3f72ebe489ea1380fe0ef Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Wed, 16 Oct 2024 12:29:51 -0700 Subject: Update support/example for ESP32-C3 to use latest versions of dependencies (#975) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Update `rtic` package to use latest version of `esp32c3` dependency * Update `rtic-macros` ESP32-C3 bindings to reflect changes in HAL * Update the ESP32-C3 examples to use latest versions of all dependencies * Update changelogs * adjust expected qemu output, add compile-time checks * remove runtime checks, this is checked at compile time * fix expected qemu output * Clean up interrupt enable code a bit * Update `rtic-monotonic` to use the latest PAC for ESP32-C3 * Update `CHANGELOG.md` for `rtic-monotonic` * ci: esp32c3: Format runner.sh * ci: esp32c3: Default to silent boot export DEBUGGING while running to get verbose boot env DEBUGGING=1 cargo xtask ... * ci: esp32c3: Update expected example output --------- Co-authored-by: onsdagens Co-authored-by: Henrik Tjäder --- rtic-monotonics/CHANGELOG.md | 4 ++++ rtic-monotonics/Cargo.toml | 2 +- rtic-monotonics/src/esp32c3.rs | 41 +++++++++++++++++------------------------ 3 files changed, 22 insertions(+), 25 deletions(-) (limited to 'rtic-monotonics') diff --git a/rtic-monotonics/CHANGELOG.md b/rtic-monotonics/CHANGELOG.md index fa185d6..6e18648 100644 --- a/rtic-monotonics/CHANGELOG.md +++ b/rtic-monotonics/CHANGELOG.md @@ -11,6 +11,10 @@ For each category, *Added*, *Changed*, *Fixed* add new entries at the top! - RP235x support +### Changed + +- Update `esp32c3` dependency + ## v2.0.2 - 2024-07-05 ### Added diff --git a/rtic-monotonics/Cargo.toml b/rtic-monotonics/Cargo.toml index 953c658..56f319f 100644 --- a/rtic-monotonics/Cargo.toml +++ b/rtic-monotonics/Cargo.toml @@ -67,7 +67,7 @@ stm32-metapac = { version = "15.0.0", optional = true } imxrt-ral = { version = "0.5.3", optional = true } -esp32c3 = {version = "0.22.0", optional = true } +esp32c3 = {version = "0.25.0", optional = true } riscv = {version = "0.11.1", optional = true } diff --git a/rtic-monotonics/src/esp32c3.rs b/rtic-monotonics/src/esp32c3.rs index 61e044e..924df2c 100644 --- a/rtic-monotonics/src/esp32c3.rs +++ b/rtic-monotonics/src/esp32c3.rs @@ -1,4 +1,4 @@ -//! [`Monotonic`](rtic_time::Monotonic) implementation for ESP32C3's SYSTIMER. +//! [`Monotonic`](rtic_time::Monotonic) implementation for ESP32-C3's SYSTIMER. //! //! Always runs at a fixed rate of 16 MHz. //! @@ -26,7 +26,7 @@ //! } //! ``` -/// Common definitions and traits for using the RP2040 timer monotonic +/// Common definitions and traits for using the ESP32-C3 timer monotonic pub mod prelude { pub use crate::esp32c3_systimer_monotonic; @@ -61,7 +61,7 @@ impl TimerBackend { .cpu_int_enable() .modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits())); //enable the CPU interupt. let intr = INTERRUPT_CORE0::ptr(); - let intr_prio_base = (*intr).cpu_int_pri_0().as_ptr(); + let intr_prio_base = (*intr).cpu_int_pri(0).as_ptr(); intr_prio_base .offset(cpu_interrupt_number) @@ -84,18 +84,11 @@ impl TimerQueueBackend for TimerBackend { peripherals .SYSTIMER .unit0_op() - .write(|w| w.timer_unit0_update().set_bit()); + .write(|w| w.update().set_bit()); // this must be polled until value is valid - while { - peripherals - .SYSTIMER - .unit0_op() - .read() - .timer_unit0_value_valid() - == false - } {} - let instant: u64 = (peripherals.SYSTIMER.unit0_value_lo().read().bits() as u64) - | ((peripherals.SYSTIMER.unit0_value_hi().read().bits() as u64) << 32); + while peripherals.SYSTIMER.unit0_op().read().value_valid() == false {} + let instant: u64 = (peripherals.SYSTIMER.unit_value(0).lo().read().bits() as u64) + | ((peripherals.SYSTIMER.unit_value(0).hi().read().bits() as u64) << 32); instant } @@ -103,19 +96,19 @@ impl TimerQueueBackend for TimerBackend { let systimer = unsafe { esp32c3::Peripherals::steal() }.SYSTIMER; systimer .target0_conf() - .write(|w| w.target0_timer_unit_sel().set_bit()); + .write(|w| w.timer_unit_sel().set_bit()); systimer .target0_conf() - .write(|w| w.target0_period_mode().clear_bit()); + .write(|w| w.period_mode().clear_bit()); systimer - .target0_lo() + .trgt(0) + .lo() .write(|w| unsafe { w.bits((instant & 0xFFFFFFFF).try_into().unwrap()) }); systimer - .target0_hi() + .trgt(0) + .hi() .write(|w| unsafe { w.bits((instant >> 32).try_into().unwrap()) }); - systimer - .comp0_load() - .write(|w| w.timer_comp0_load().set_bit()); //sync period to comp register + systimer.comp0_load().write(|w| w.load().set_bit()); //sync period to comp register systimer.conf().write(|w| w.target0_work_en().set_bit()); systimer.int_ena().write(|w| w.target0().set_bit()); } @@ -129,13 +122,13 @@ impl TimerQueueBackend for TimerBackend { fn pend_interrupt() { extern "C" { - fn cpu_int_31_handler(); + fn interrupt31(); } //run the timer interrupt handler in a critical section to emulate a max priority //interrupt. //since there is no hardware support for pending a timer interrupt. riscv::interrupt::disable(); - unsafe { cpu_int_31_handler() }; + unsafe { interrupt31() }; unsafe { riscv::interrupt::enable() }; } @@ -162,7 +155,7 @@ macro_rules! esp32c3_systimer_monotonic { /// /// This method must be called only once. pub fn start(timer: esp32c3::SYSTIMER) { - #[export_name = "cpu_int_31_handler"] + #[export_name = "interrupt31"] #[allow(non_snake_case)] unsafe extern "C" fn Systimer() { use $crate::TimerQueueBackend; -- cgit v1.2.3