From b97bc791260554edfd79dbd84c05815bef26b636 Mon Sep 17 00:00:00 2001
From: Wouter Geraedts <git@woutergeraedts.nl>
Date: Tue, 9 Apr 2024 15:01:27 +0200
Subject: Added esp32c6 support and example

---
 xtask/src/argument_parsing.rs | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

(limited to 'xtask')

diff --git a/xtask/src/argument_parsing.rs b/xtask/src/argument_parsing.rs
index a9af170..2ce1503 100644
--- a/xtask/src/argument_parsing.rs
+++ b/xtask/src/argument_parsing.rs
@@ -146,6 +146,7 @@ pub enum Backends {
     Thumbv8Base,
     Thumbv8Main,
     RiscvEsp32C3,
+    RiscvEsp32C6,
     Riscv32ImcClint,
     Riscv32ImcMecall,
     Riscv32ImacClint,
@@ -163,7 +164,9 @@ impl Backends {
             Backends::Riscv32ImcClint | Backends::Riscv32ImcMecall | Backends::RiscvEsp32C3 => {
                 RISCV32IMC
             }
-            Backends::Riscv32ImacClint | Backends::Riscv32ImacMecall => RISCV32IMAC,
+            Backends::Riscv32ImacClint | Backends::Riscv32ImacMecall | Backends::RiscvEsp32C6 => {
+                RISCV32IMAC
+            }
         }
     }
 
@@ -175,6 +178,7 @@ impl Backends {
             Backends::Thumbv8Base => "thumbv8base-backend",
             Backends::Thumbv8Main => "thumbv8main-backend",
             Backends::RiscvEsp32C3 => "riscv-esp32c3-backend",
+            Backends::RiscvEsp32C6 => "riscv-esp32c6-backend",
             Backends::Riscv32ImcClint | Backends::Riscv32ImacClint => "riscv-clint-backend",
             Backends::Riscv32ImcMecall | Backends::Riscv32ImacMecall => "riscv-mecall-backend",
         }
@@ -186,6 +190,7 @@ impl Backends {
             Backends::Thumbv6 | Backends::Thumbv8Base => "cortex-m-source-masking",
             Backends::Thumbv7 | Backends::Thumbv8Main => "cortex-m-basepri",
             Backends::RiscvEsp32C3 => "riscv-esp32c3",
+            Backends::RiscvEsp32C6 => "riscv-esp32c6",
             Backends::Riscv32ImcClint | Backends::Riscv32ImacClint => "riscv-clint",
             Backends::Riscv32ImcMecall | Backends::Riscv32ImacMecall => "riscv-mecall",
         }
@@ -243,6 +248,7 @@ pub enum BuildOrCheck {
 #[derive(clap::ValueEnum, Copy, Clone, Default, Debug)]
 pub enum Platforms {
     Esp32C3,
+    Esp32C6,
     Hifive1,
     #[default]
     Lm3s6965,
@@ -257,6 +263,7 @@ impl Platforms {
     pub fn name(&self) -> String {
         let name = match self {
             Platforms::Esp32C3 => "esp32c3",
+            Platforms::Esp32C6 => "esp32c6",
             Platforms::Hifive1 => "hifive1",
             Platforms::Lm3s6965 => "lm3s6965",
             Platforms::Nrf52840 => "nrf52840",
@@ -272,7 +279,7 @@ impl Platforms {
     pub fn rust_flags(&self) -> Vec<String> {
         let c = "-C".to_string();
         match self {
-            Platforms::Esp32C3 => vec![c, "link-arg=-Tlinkall.x".to_string()],
+            Platforms::Esp32C3 | Platforms::Esp32C6 => vec![c, "link-arg=-Tlinkall.x".to_string()],
             Platforms::Hifive1 => vec![c, "link-arg=-Thifive1-link.x".to_string()],
             Platforms::Lm3s6965 => vec![c, "link-arg=-Tlink.x".to_string()],
             Platforms::Nrf52840 => vec![
@@ -311,6 +318,7 @@ impl Platforms {
     pub fn default_backend(&self) -> Backends {
         match self {
             Platforms::Esp32C3 => Backends::RiscvEsp32C3,
+            Platforms::Esp32C6 => Backends::RiscvEsp32C6,
             Platforms::Hifive1 => Backends::Riscv32ImcClint,
             Platforms::Lm3s6965 => Backends::Thumbv7,
             Platforms::Nrf52840 => unimplemented!(),
@@ -330,6 +338,10 @@ impl Platforms {
                 RISCV32IMC => Ok(None),
                 _ => Err(()),
             },
+            Platforms::Esp32C6 => match backend.to_target() {
+                RISCV32IMAC => Ok(None),
+                _ => Err(()),
+            },
             Platforms::Hifive1 => match backend.to_target() {
                 RISCV32IMC => Ok(None),
                 _ => Err(()),
-- 
cgit v1.2.3