[breaking-change] Factor out "sram" resource.

Fixes #9.

4 files changed, 30 insertions, 28 deletions

diff --git a/nmigen_boards/blackice.py b/nmigen_boards/blackice.py
index aa84d5e..51d09e4 100644
--- a/nmigen_boards/blackice.py
+++ b/nmigen_boards/blackice.py
@@ -41,19 +41,11 @@ class BlackIcePlatform(LatticeICE40Platform):
             attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
         ),
 
-        Resource("sram", 0,
-            Subsignal("address", Pins(
-                "137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
-                dir="o"
-            )),
-            Subsignal("data", Pins(
-                "135 134 130 128 125 124 122 121 61 60 56 55 52 49 48 47",
-                dir="io"
-            )),
-            Subsignal("oe", PinsN("45", dir="o")),
-            Subsignal("we", PinsN("120", dir="o")),
-            Subsignal("cs", PinsN("136", dir="o")),
-            Attrs(IO_STANDARD="SB_LVCMOS33"),
+        SRAMResource(0,
+            cs="136", oe="45", we="120",
+            a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
+            d="135 134 130 128 125 124 122 121 61 60 56 55 52 49 48 47",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS33"),
         ),
     ]
     connectors  = [
diff --git a/nmigen_boards/blackice_ii.py b/nmigen_boards/blackice_ii.py
index b17221c..040a8f8 100644
--- a/nmigen_boards/blackice_ii.py
+++ b/nmigen_boards/blackice_ii.py
@@ -41,21 +41,12 @@ class BlackIceIIPlatform(LatticeICE40Platform):
             attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
         ),
 
-        Resource("sram", 0,
-            Subsignal("address", Pins(
-                "137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
-                dir="o"
-            )),
-            Subsignal("data", Pins(
-                "136 135 134 130 125 124 122 121 62 61 60 56 55 48 47 45",
-                dir="io"
-            )),
-            Subsignal("oe", PinsN("29", dir="o")),
-            Subsignal("we", PinsN("120", dir="o")),
-            Subsignal("cs", PinsN("136", dir="o")),
-            Subsignal("ub", PinsN("28", dir="o")),
-            Subsignal("lb", PinsN("24", dir="o")),
-            Attrs(IO_STANDARD="SB_LVCMOS33"),
+        SRAMResource(0,
+            cs="136", oe="29", we="120",
+            a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
+            d="136 135 134 130 125 124 122 121 62 61 60 56 55 48 47 45",
+            dm="24 28",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS33"),
         ),
     ]
     connectors  = [
diff --git a/nmigen_boards/dev/__init__.py b/nmigen_boards/dev/__init__.py
index 1af4fe2..242b0f9 100644
--- a/nmigen_boards/dev/__init__.py
+++ b/nmigen_boards/dev/__init__.py
@@ -1,3 +1,4 @@
 from .uart import UARTResource
 from .flash import SPIFlashResources
 from .spi import SPIResource
+from .sram import SRAMResource
diff --git a/nmigen_boards/dev/sram.py b/nmigen_boards/dev/sram.py
new file mode 100644
index 0000000..4e2cd91
--- /dev/null
+++ b/nmigen_boards/dev/sram.py
@@ -0,0 +1,18 @@
+from nmigen.build import *
+
+
+__all__ = ["SRAMResource"]
+
+
+def SRAMResource(*args, cs, oe, we, a, d, dm=None, attrs=None):
+    io = []
+    io.append(Subsignal("cs", PinsN(cs, dir="o")))
+    io.append(Subsignal("oe", PinsN(oe, dir="o")))
+    io.append(Subsignal("we", PinsN(we, dir="o")))
+    io.append(Subsignal("a", Pins(a, dir="o")))
+    io.append(Subsignal("d", Pins(d, dir="io")))
+    if dm is not None:
+        io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#"
+    if attrs is not None:
+        io.append(attrs)
+    return Resource.family(*args, default_name="sram", ios=io)