diff options
| author | whitequark <whitequark@whitequark.org> | 2019-10-03 06:10:43 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-10-03 06:16:18 +0000 |
| commit | 50acf4a72433a22bbe6a8162deb7b959370a0a15 (patch) | |
| tree | 770bbba1604d006c2e6faffcbd0b261360c4c309 | |
| parent | c7c637043817eae6f48c33b707b40c9c1b20f199 (diff) | |
[breaking-change] Fix polarity of "dm" signal in "memory" resource.
LB# and UB# enable writing their corresponding byte. The "m" in "dm"
means mask; that is, logical high masks (prevents) the byte from
being written. This means that it should use Pins(), not PinsN(),
to get the behavior implied by "mask".
| -rw-r--r-- | nmigen_boards/resources/memory.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py index 809035c..33976a7 100644 --- a/nmigen_boards/resources/memory.py +++ b/nmigen_boards/resources/memory.py @@ -90,7 +90,7 @@ def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None): io.append(Subsignal("a", Pins(a, dir="o"))) io.append(Subsignal("d", Pins(d, dir="io"))) if dm is not None: - io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#" + io.append(Subsignal("dm", Pins(dm, dir="o"))) # dm="LB# UB#" if attrs is not None: io.append(attrs) return Resource.family(*args, default_name="sram", ios=io) |