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authorJean THOMAS <git0@pub.jeanthomas.me>2020-08-03 13:27:04 +0200
committerGitHub <noreply@github.com>2020-08-03 13:27:04 +0200
commit550f9c62e450d8b5982dffb034afe8122aa3a8a0 (patch)
tree6d2db060dc88873d6315cfdb44074e8d440c2de6
parentb836269225359af44c96c2f52b35db0453252446 (diff)
ecpix5: add termination attributes to DDR3 signals
-rw-r--r--nmigen_boards/ecpix5.py6
1 files changed, 4 insertions, 2 deletions
diff --git a/nmigen_boards/ecpix5.py b/nmigen_boards/ecpix5.py
index 50c2616..8f0bf7a 100644
--- a/nmigen_boards/ecpix5.py
+++ b/nmigen_boards/ecpix5.py
@@ -68,8 +68,10 @@ class _ECPIX5Platform(LatticeECP5Platform):
Subsignal("cas", PinsN("P2", dir="o")),
Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")),
Subsignal("ba", Pins("U6 N3 N4", dir="o")),
- Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")),
- Subsignal("dq", Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2", dir="io")),
+ Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"),
+ Attrs(IO_TYPE="SSTL135D_I", TERMINATION="OFF", DIFFRESISTOR="100")),
+ Subsignal("dq", Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2", dir="io"),
+ Attrs(TERMINATION="75")),
Subsignal("dm", Pins("U4 U1", dir="o")),
Subsignal("odt", Pins("P3", dir="o")),
Attrs(IO_TYPE="SSTL135_I")