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authorMariusz Glebocki <mglb@arccos-1.net>2020-08-25 16:29:28 +0200
committerGitHub <noreply@github.com>2020-08-25 14:29:28 +0000
commit8be37da521e8789726a53bd4e0c261c12e2ab22b (patch)
tree3c30b1689823ebc243d5d33ea7bb3c3d9c93aa13
parentd20fb96e358994eb06295b3b64ee1efe13d86004 (diff)
arty_a7: fix `rst` pin polarity.
-rw-r--r--nmigen_boards/arty_a7.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/nmigen_boards/arty_a7.py b/nmigen_boards/arty_a7.py
index 7e7e628..9fb0842 100644
--- a/nmigen_boards/arty_a7.py
+++ b/nmigen_boards/arty_a7.py
@@ -18,7 +18,7 @@ class ArtyA7Platform(Xilinx7SeriesPlatform):
resources = [
Resource("clk100", 0, Pins("E3", dir="i"),
Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),
- Resource("rst", 0, Pins("C2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
+ Resource("rst", 0, PinsN("C2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
*LEDResources(pins="H5 J5 T9 T10", attrs=Attrs(IOSTANDARD="LVCMOS33")),