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| author | Ivan Grokhotkov <ivan@espressif.com> | 2020-06-08 23:21:33 +0200 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-11 14:10:55 +0000 |
| commit | ea2ac2b10658b8349cc307b28a316a0c8917b452 (patch) | |
| tree | d9f79472727bd9bfd0f6962409cc196bc83d0b50 /nmigen_boards/de0.py | |
| parent | f3957586e210d6d7c7c40b8b4080107c28c1c744 (diff) | |
de0: fix UART RTS/CTS direction.
RTS and CTS match the schematic, but the direction is incorrect:
CTS is output, RTS is input. Fix by setting role=dce.
Ref. https://www.intel.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-5804152209-de0-user-manual.pdf
Diffstat (limited to 'nmigen_boards/de0.py')
| -rw-r--r-- | nmigen_boards/de0.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/nmigen_boards/de0.py b/nmigen_boards/de0.py index 8574230..5ba3e9a 100644 --- a/nmigen_boards/de0.py +++ b/nmigen_boards/de0.py @@ -44,7 +44,8 @@ class DE0Platform(IntelPlatform): UARTResource(0, rx="U22", tx="U21", rts="V22", cts="V21", - attrs=Attrs(io_standard="3.3-V LVTTL")), + attrs=Attrs(io_standard="3.3-V LVTTL"), + role="dce"), Resource("display_hd44780", 0, Subsignal("e", Pins("E21", dir="o")), |