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authorwhitequark <whitequark@whitequark.org>2019-08-03 16:19:03 +0000
committerwhitequark <whitequark@whitequark.org>2019-08-03 16:20:16 +0000
commitd5bea94b228b956cfd119af9415fbb0e3abc53ac (patch)
treec39b98fa6809d889d419638dce691b1eb0f45c13 /nmigen_boards/icebreaker.py
parentbc2d42e451d7b866f0a28c1c3888a8b54ed219d2 (diff)
Update all boards to use default_clk.
Diffstat (limited to 'nmigen_boards/icebreaker.py')
-rw-r--r--nmigen_boards/icebreaker.py9
1 files changed, 5 insertions, 4 deletions
diff --git a/nmigen_boards/icebreaker.py b/nmigen_boards/icebreaker.py
index 39d82d5..a62ecdc 100644
--- a/nmigen_boards/icebreaker.py
+++ b/nmigen_boards/icebreaker.py
@@ -10,9 +10,10 @@ __all__ = ["ICEBreakerPlatform"]
class ICEBreakerPlatform(LatticeICE40Platform):
- device = "iCE40UP5K"
- package = "SG48"
- resources = [
+ device = "iCE40UP5K"
+ package = "SG48"
+ default_clk = "clk12"
+ resources = [
Resource("clk12", 0, Pins("35", dir="i"),
Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
@@ -85,4 +86,4 @@ if __name__ == "__main__":
from ._blinky import Blinky
p = ICEBreakerPlatform()
p.add_resources(p.break_off_pmod)
- p.build(Blinky("clk12"), do_program=True)
+ p.build(Blinky(), do_program=True)