diff options
| author | whitequark <whitequark@whitequark.org> | 2019-08-03 16:19:03 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-08-03 16:20:16 +0000 |
| commit | d5bea94b228b956cfd119af9415fbb0e3abc53ac (patch) | |
| tree | c39b98fa6809d889d419638dce691b1eb0f45c13 /nmigen_boards/icestick.py | |
| parent | bc2d42e451d7b866f0a28c1c3888a8b54ed219d2 (diff) | |
Update all boards to use default_clk.
Diffstat (limited to 'nmigen_boards/icestick.py')
| -rw-r--r-- | nmigen_boards/icestick.py | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/nmigen_boards/icestick.py b/nmigen_boards/icestick.py index e575aac..bdeb112 100644 --- a/nmigen_boards/icestick.py +++ b/nmigen_boards/icestick.py @@ -11,9 +11,10 @@ __all__ = ["ICEStickPlatform"] class ICEStickPlatform(LatticeICE40Platform): - device = "iCE40HX1K" - package = "TQ144" - resources = [ + device = "iCE40HX1K" + package = "TQ144" + default_clk = "clk12" + resources = [ Resource("clk12", 0, Pins("21", dir="i"), Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")), @@ -38,7 +39,7 @@ class ICEStickPlatform(LatticeICE40Platform): attrs=Attrs(IO_STANDARD="SB_LVCMOS33") ), ] - connectors = [ + connectors = [ Connector("pmod", 0, "78 79 80 81 - - 87 88 90 91 - -"), # J2 Connector("j", 1, "- - 112 113 114 115 116 117 118 119"), # J1 @@ -53,4 +54,4 @@ class ICEStickPlatform(LatticeICE40Platform): if __name__ == "__main__": from ._blinky import build_and_program - build_and_program(ICEStickPlatform, "clk12") + build_and_program(ICEStickPlatform) |