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authorwhitequark <whitequark@whitequark.org>2019-08-03 16:19:03 +0000
committerwhitequark <whitequark@whitequark.org>2019-08-03 16:20:16 +0000
commitd5bea94b228b956cfd119af9415fbb0e3abc53ac (patch)
treec39b98fa6809d889d419638dce691b1eb0f45c13 /nmigen_boards/kc705.py
parentbc2d42e451d7b866f0a28c1c3888a8b54ed219d2 (diff)
Update all boards to use default_clk.
Diffstat (limited to 'nmigen_boards/kc705.py')
-rw-r--r--nmigen_boards/kc705.py13
1 files changed, 7 insertions, 6 deletions
diff --git a/nmigen_boards/kc705.py b/nmigen_boards/kc705.py
index 22ba5fc..91e4a5b 100644
--- a/nmigen_boards/kc705.py
+++ b/nmigen_boards/kc705.py
@@ -10,10 +10,11 @@ __all__ = ["KC705Platform"]
class KC705Platform(Xilinx7SeriesPlatform):
- device = "xc7k325t"
- package = "ffg900"
- speed = "2"
- resources = [
+ device = "xc7k325t"
+ package = "ffg900"
+ speed = "2"
+ default_clk = "clk156"
+ resources = [
Resource("clk156", 0, DiffPairs("K28", "K29", dir="i"),
Clock(156e6), Attrs(IOSTANDARD="LVDS_25")),
@@ -31,7 +32,7 @@ class KC705Platform(Xilinx7SeriesPlatform):
attrs=Attrs(IOSTANDARD="LVCMOS33")
),
]
- connectors = []
+ connectors = []
def toolchain_program(self, products, name):
openocd = os.environ.get("OPENOCD", "openocd")
@@ -44,4 +45,4 @@ class KC705Platform(Xilinx7SeriesPlatform):
if __name__ == "__main__":
from ._blinky import build_and_program
- build_and_program(KC705Platform, "clk156")
+ build_and_program(KC705Platform)