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authorGwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>2020-07-13 17:43:50 +0200
committerwhitequark <whitequark@whitequark.org>2020-07-13 15:53:19 +0000
commit2cd86c1f61a5380e428e67430e5b81ff9dcd0f96 (patch)
tree616c538707d375db85cbf744c41ccd11b8e1435e /nmigen_boards/orangecrab_r0_2.py
parent856f712e9c8561f5642eee9d4e890fa04de4170e (diff)
orangecrab_r0_2: IO_STANDARD -> IO_TYPE
Diffstat (limited to 'nmigen_boards/orangecrab_r0_2.py')
-rw-r--r--nmigen_boards/orangecrab_r0_2.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/nmigen_boards/orangecrab_r0_2.py b/nmigen_boards/orangecrab_r0_2.py
index 474b198..e427840 100644
--- a/nmigen_boards/orangecrab_r0_2.py
+++ b/nmigen_boards/orangecrab_r0_2.py
@@ -17,7 +17,7 @@ class OrangeCrabR0_2Platform(LatticeECP5Platform):
default_clk = "clk"
resources = [
Resource("clk", 0, Pins("A9", dir="i"),
- Clock(48e6), Attrs(IO_STANDARD="LVCMOS33")),
+ Clock(48e6), Attrs(IO_TYPE="LVCMOS33")),
# Used to reload FPGA configuration.
# Can enter USB bootloader by assigning button 0 to program.
@@ -33,7 +33,7 @@ class OrangeCrabR0_2Platform(LatticeECP5Platform):
*SPIFlashResources(0,
cs="U17", clk="U16", miso="T18", mosi="U18", wp="R18", hold="N18",
- attrs=Attrs(IO_STANDARD="LVCMOS33"),
+ attrs=Attrs(IO_TYPE="LVCMOS33"),
),
Resource("ddr3", 0,