Factor out DDR3.

1 files changed, 25 insertions, 0 deletions

diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py
index a363068..c7c476c 100644
--- a/nmigen_boards/resources/memory.py
+++ b/nmigen_boards/resources/memory.py
@@ -4,6 +4,7 @@ from nmigen.build import *
 __all__ = [
     "SPIFlashResources", "SDCardResources",
     "SRAMResource", "SDRAMResource", "NORFlashResources",
+    "DDR3Resource",
 ]
 
 
@@ -163,3 +164,27 @@ def NORFlashResources(*args, rst=None, byte_n=None, cs_n, oe_n, we_n, wp_n, by,
                                          name_suffix="16bit"))
 
     return resources
+
+
+def DDR3Resource(*args, rst_n=None, clk_p, clk_n, clk_en, cs_n, we_n, ras_n, cas_n, a, ba, dqs_p, dqs_n, dq, dm, odt,
+                 conn=None, diff_attrs=None, attrs=None):
+    ios = []
+
+    ios.append(Subsignal("rst", PinsN(rst_n, dir="o", conn=conn, assert_width=1)))
+    ios.append(Subsignal("clk", DiffPairs(clk_p, clk_n, dir="o", conn=conn, assert_width=1), diff_attrs))
+    ios.append(Subsignal("clk_en", Pins(clk_en, dir="o", conn=conn, assert_width=1)))
+    ios.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+    ios.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
+    ios.append(Subsignal("ras", PinsN(ras_n, dir="o", conn=conn, assert_width=1)))
+    ios.append(Subsignal("cas", PinsN(cas_n, dir="o", conn=conn, assert_width=1)))
+    ios.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
+    ios.append(Subsignal("ba", Pins(ba, dir="o", conn=conn)))
+    ios.append(Subsignal("dqs", DiffPairs(dqs_p, dqs_n, dir="io", conn=conn), diff_attrs))
+    ios.append(Subsignal("dq", Pins(dq, dir="io", conn=conn)))
+    ios.append(Subsignal("dm", Pins(dm, dir="o", conn=conn)))
+    ios.append(Subsignal("odt", Pins(odt, dir="o", conn=conn, assert_width=1)))
+
+    if attrs is not None:
+        ios.append(attrs)
+
+    return Resource.family(*args, default_name="ddr3", ios=ios)