Rename nMigen to Amaranth HDL.

1 files changed, 5 insertions, 34 deletions

diff --git a/nmigen_boards/upduino_v1.py b/nmigen_boards/upduino_v1.py
index a24a7a7..eeb0995 100644
--- a/nmigen_boards/upduino_v1.py
+++ b/nmigen_boards/upduino_v1.py
@@ -1,36 +1,7 @@
-from nmigen.build import *
-from nmigen.vendor.lattice_ice40 import *
-from .resources import *
+from amaranth_boards.upduino_v1 import *
+from amaranth_boards.upduino_v1 import __all__
 
 
-__all__ = ["UpduinoV1Platform"]
-
-
-class UpduinoV1Platform(LatticeICE40Platform):
-    device      = "iCE40UP5K"
-    package     = "SG48"
-    default_clk = "SB_HFOSC"
-    hfosc_div   = 0
-    resources   = [
-        *LEDResources(pins="39 40 41", invert=True,
-                      attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
-        Resource("led_g", 0, PinsN("39", dir="o"),
-                 Attrs(IO_STANDARD="SB_LVCMOS")),
-        Resource("led_b", 0, PinsN("40", dir="o"),
-                 Attrs(IO_STANDARD="SB_LVCMOS")),
-        Resource("led_r", 0, PinsN("41", dir="o"),
-                 Attrs(IO_STANDARD="SB_LVCMOS")),
-
-        *SPIFlashResources(0,
-            cs_n="16", clk="15", cipo="17", copi="14",
-            attrs=Attrs(IO_STANDARD="SB_LVCMOS")
-        ),
-    ]
-    connectors  = [
-        # "Left" row of header pins (JP5 on the schematic)
-        Connector("j", 0, "- - 23 25 26 27 32 35 31 37 34 43 36 42 38 28"),
-        # "Right" row of header pins (JP6 on the schematic)
-        Connector("j", 1, "12 21 13 19 18 11 9 6 44 4 3 48 45 47 46 2")
-    ]
-
-    # This board doesn't have an integrated programmer.
+import warnings
+warnings.warn("instead of nmigen_boards.upduino_v1, use amaranth_boards.upduino_v1",
+              DeprecationWarning, stacklevel=2)