diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2021-08-12 20:24:20 +0200 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-08-13 07:39:41 +0000 |
| commit | 306890f884815835f90bf7099242b450a92d3600 (patch) | |
| tree | c561d9c41e32ea41799a3b4b8d46c150bd47c7f3 /nmigen_boards | |
| parent | 84ffc81e80a337111f8fab63b50159e86d6a8e85 (diff) | |
nexys3ddr: Fix I/O voltage for SW8 and SW9
As can be seen in the schematics for the Nexys4DDR board, the switches
SW8 and SW9 are connected to the 1.8V rail, rather than 3.3V.
Diffstat (limited to 'nmigen_boards')
| -rw-r--r-- | nmigen_boards/nexys4ddr.py | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/nmigen_boards/nexys4ddr.py b/nmigen_boards/nexys4ddr.py index 522b8a3..cce8b9e 100644 --- a/nmigen_boards/nexys4ddr.py +++ b/nmigen_boards/nexys4ddr.py @@ -22,8 +22,13 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform): PinsN("C12", dir="i"), Attrs(IOSTANDARD="LVCMOS33")), *SwitchResources( - pins="J15 L16 M13 R15 R17 T18 U18 R13 T8 U8 R16 T13 H6 U12 U11 V10", + pins={0: 'J15', 1: 'L16', 2: 'M13', 3: 'R15', 4: 'R17', 5: 'T18', + 6: 'U18', 7: 'R13', 10: 'R16', 11: 'T13', 12: 'H6', + 13: 'U12', 14: 'U11', 15: 'V10'}, attrs=Attrs(IOSTANDARD="LVCMOS33")), + *SwitchResources( + pins={8: 'T8', 9: 'U8'}, + attrs=Attrs(IOSTANDARD="LVCMOS18")), *LEDResources( pins="H17 K15 J13 N14 R18 V17 U17 U16 V16 T15 U14 T16 V15 V14 V12 V11", |