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authorwhitequark <whitequark@whitequark.org>2019-07-03 09:54:39 +0000
committerwhitequark <whitequark@whitequark.org>2019-07-03 09:54:45 +0000
commit6e0cc9d2c9c085912d5350f1f88aaa68af1e25d8 (patch)
tree9a2df193d9182ff88c86d7bdad0caf5e3c7c2d24 /nmigen_boards
parent7dfe0be7a5b2e75dbe0cee4fc03ce9d681449930 (diff)
dev.uart: fix typo.
Diffstat (limited to 'nmigen_boards')
-rw-r--r--nmigen_boards/dev/uart.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/nmigen_boards/dev/uart.py b/nmigen_boards/dev/uart.py
index df03bd1..495dbcf 100644
--- a/nmigen_boards/dev/uart.py
+++ b/nmigen_boards/dev/uart.py
@@ -8,7 +8,7 @@ def UARTResource(number, *, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=
attrs=None):
io = []
io.append(Subsignal("rx", Pins(rx, dir="i")))
- io.append(Subsignal("tx", Pins(rx, dir="o")))
+ io.append(Subsignal("tx", Pins(tx, dir="o")))
if rts is not None:
io.append(Subsignal("rts", Pins(rts, dir="o")))
if cts is not None:
@@ -32,7 +32,7 @@ def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
assert (en is not None) ^ (sd is not None)
io = []
io.append(Subsignal("rx", Pins(rx, dir="i")))
- io.append(Subsignal("tx", Pins(rx, dir="o")))
+ io.append(Subsignal("tx", Pins(tx, dir="o")))
if en is not None:
io.append(Subsignal("en", Pins(en, dir="o")))
if sd is not None: