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authorIvan Grokhotkov <ivan@espressif.com>2020-06-08 23:23:42 +0200
committerwhitequark <whitequark@whitequark.org>2020-06-11 14:10:55 +0000
commit70897161bf7846d940490ebd5198aef1f6800919 (patch)
treed77b5d6ef11ccccc670dd44b81fbd42db33f6b85 /nmigen_boards
parentea2ac2b10658b8349cc307b28a316a0c8917b452 (diff)
[breaking-change] ice40_hx8k_b_evn: fix UART flow control pins.
RTS/CTS and DTR/DSR pairs have been swapped to work around the signal direction in UARTResource. Un-reverse the signals, making the names match the schematic. Fix the direction by setting role=dce. Ref. http://www.latticesemi.com/view_document?document_id=50373
Diffstat (limited to 'nmigen_boards')
-rw-r--r--nmigen_boards/ice40_hx8k_b_evn.py5
1 files changed, 3 insertions, 2 deletions
diff --git a/nmigen_boards/ice40_hx8k_b_evn.py b/nmigen_boards/ice40_hx8k_b_evn.py
index 07c5348..48d5d9e 100644
--- a/nmigen_boards/ice40_hx8k_b_evn.py
+++ b/nmigen_boards/ice40_hx8k_b_evn.py
@@ -23,8 +23,9 @@ class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
), # D2..D9
UARTResource(0,
- rx="B10", tx="B12", rts="A15", cts="B13", dtr="B14", dsr="A16", dcd="B15",
- attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
+ rx="B10", tx="B12", rts="B13", cts="A15", dtr="A16", dsr="B14", dcd="B15",
+ attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1),
+ role="dce"
),
*SPIFlashResources(0,