[breaking-change] Factor out "serial" resource and rename to "uart".

Also, add missing pullups where appropriate.

7 files changed, 44 insertions, 30 deletions

diff --git a/nmigen_boards/blackice.py b/nmigen_boards/blackice.py
index 91c1e01..399e29c 100644
--- a/nmigen_boards/blackice.py
+++ b/nmigen_boards/blackice.py
@@ -3,6 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
+from .dev import *
 
 
 __all__ = ["BlackIcePlatform"]
@@ -34,12 +35,9 @@ class BlackIcePlatform(LatticeICE40Platform):
         Resource("user_sw", 2, PinsN("39", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
         Resource("user_sw", 3, PinsN("41", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
 
-        Resource("serial", 0,
-            Subsignal("rx", Pins("88", dir="i")),
-            Subsignal("tx", Pins("85", dir="o")),
-            Subsignal("rts", Pins("91", dir="o")),
-            Subsignal("cts", Pins("94", dir="i")),
-            Attrs(IO_STANDARD="SB_LVCMOS33"),
+        UARTResource(0,
+            rx="88", tx="85", rts="91", cts="94",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
         ),
 
         Resource("sram", 0,
diff --git a/nmigen_boards/blackice_ii.py b/nmigen_boards/blackice_ii.py
index ad8cf0f..35f3fe6 100644
--- a/nmigen_boards/blackice_ii.py
+++ b/nmigen_boards/blackice_ii.py
@@ -34,12 +34,9 @@ class BlackIceIIPlatform(LatticeICE40Platform):
         Resource("user_sw", 2, PinsN("39", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
         Resource("user_sw", 3, PinsN("41", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
 
-        Resource("serial", 0,
-            Subsignal("rx", Pins("88", dir="i")),
-            Subsignal("tx", Pins("85", dir="o")),
-            Subsignal("rts", Pins("91", dir="o")),
-            Subsignal("cts", Pins("94", dir="i")),
-            Attrs(IO_STANDARD="SB_LVCMOS33"),
+        UARTResource(0,
+            rx="88", tx="85", rts="91", cts="94",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
         ),
 
         Resource("sram", 0,
diff --git a/nmigen_boards/dev/__init__.py b/nmigen_boards/dev/__init__.py
index b27acfa..f89e46a 100644
--- a/nmigen_boards/dev/__init__.py
+++ b/nmigen_boards/dev/__init__.py
@@ -1 +1,2 @@
+from .uart import UARTResource
 from .flash import SPIFlashResources
diff --git a/nmigen_boards/dev/uart.py b/nmigen_boards/dev/uart.py
new file mode 100644
index 0000000..27d1c81
--- /dev/null
+++ b/nmigen_boards/dev/uart.py
@@ -0,0 +1,26 @@
+from nmigen.build import *
+
+
+__all__ = ["UARTResource"]
+
+
+def UARTResource(number, *, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
+                 attrs=None):
+    io = []
+    io.append(Subsignal("rx", Pins(rx, dir="i")))
+    io.append(Subsignal("tx", Pins(rx, dir="o")))
+    if rts is not None:
+        io.append(Subsignal("rts", Pins(rts, dir="o")))
+    if cts is not None:
+        io.append(Subsignal("cts", Pins(cts, dir="i")))
+    if dtr is not None:
+        io.append(Subsignal("dtr", Pins(dtr, dir="o")))
+    if dsr is not None:
+        io.append(Subsignal("dsr", Pins(dsr, dir="i")))
+    if dcd is not None:
+        io.append(Subsignal("dcd", Pins(dcd, dir="i")))
+    if ri is not None:
+        io.append(Subsignal("ri", Pins(ri, dir="i")))
+    if attrs is not None:
+        io.append(attrs)
+    return Resource("uart", number, *io)
diff --git a/nmigen_boards/icebreaker.py b/nmigen_boards/icebreaker.py
index b3c594b..5032346 100644
--- a/nmigen_boards/icebreaker.py
+++ b/nmigen_boards/icebreaker.py
@@ -24,10 +24,9 @@ class ICEBreakerPlatform(LatticeICE40Platform):
 
         Resource("user_btn",  0, PinsN("10", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
 
-        Resource("serial", 0,
-            Subsignal("rx",  Pins("6", dir="i")),
-            Subsignal("tx",  Pins("9", dir="o"), Attrs(PULLUP="1")),
-            Attrs(IO_STANDARD="SB_LVTTL")
+        UARTResource(0,
+            rx="6", tx="9",
+            attrs=Attrs(IO_STANDARD="SB_LVTTL", PULLUP="1")
         ),
 
         *SPIFlashResources(0,
diff --git a/nmigen_boards/icestick.py b/nmigen_boards/icestick.py
index 778ad2d..5d0dd4b 100644
--- a/nmigen_boards/icestick.py
+++ b/nmigen_boards/icestick.py
@@ -22,15 +22,9 @@ class ICEStickPlatform(LatticeICE40Platform):
         Resource("user_led", 3, Pins("96", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
         Resource("user_led", 4, Pins("95", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
 
-        Resource("serial", 0,
-            Subsignal("rx",  Pins("9", dir="i")),
-            Subsignal("tx",  Pins("8", dir="o")),
-            Subsignal("rts", Pins("7", dir="o")),
-            Subsignal("cts", Pins("4", dir="i")),
-            Subsignal("dtr", Pins("3", dir="o")),
-            Subsignal("dsr", Pins("2", dir="i")),
-            Subsignal("dcd", Pins("1", dir="i")),
-            Attrs(IO_STANDARD="SB_LVTTL", PULLUP="1")
+        UARTResource(0,
+            rx="9", tx="8", rts="7", cts="4", dtr="3", dsr="2", dcd="1",
+            attrs=Attrs(IO_STANDARD="SB_LVTTL", PULLUP="1")
         ),
 
         Resource("irda", 0,
diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py
index 9216849..6d1c41a 100644
--- a/nmigen_boards/versa_ecp5.py
+++ b/nmigen_boards/versa_ecp5.py
@@ -57,15 +57,14 @@ class VersaECP5Platform(LatticeECP5Platform):
         Resource("user_sw", 6, PinsN("K19", dir="i"), Attrs(IO_TYPE="LVCMOS25")),
         Resource("user_sw", 7, PinsN("K20", dir="i"), Attrs(IO_TYPE="LVCMOS25")),
 
-        Resource("serial", 0,
-            Subsignal("rx", Pins("C11", dir="i")),
-            Subsignal("tx", Pins("A11", dir="o")),
-            Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
+        UARTResource(0,
+            rx="C11", tx="A11",
+            attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
         ),
 
         *SPIFlashResources(0,
             cs="R2", clk="U3", miso="W2", mosi="V2", wp="Y2", hold="W1",
-            attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
+            attrs=Attrs(IO_STANDARD="LVCMOS33")
         ),
 
         Resource("eth_clk125",     0, Pins("L19"),