[breaking-change] Add `_n` suffix to argument names of pins with fixed inverters.

Note: this change does NOT affect pin functionality or naming, and
does not require modifying your design. It does however affect some
board files, where keywords corresponding to active low pins will have
to be adjusted:
    SPIResource(0, cs="C1", ...) → SPIResource(0, cs_n="C1", ...)

The new naming scheme will make it easier to write and audit board
files by clearly marking inverted pins in resource factories, similarly to
how `PinsN` indicates the same in bare resources.

Fixes #129.

38 files changed, 82 insertions, 82 deletions

diff --git a/nmigen_boards/arty_a7.py b/nmigen_boards/arty_a7.py
index 9fb0842..3f72f0a 100644
--- a/nmigen_boards/arty_a7.py
+++ b/nmigen_boards/arty_a7.py
@@ -36,7 +36,7 @@ class ArtyA7Platform(Xilinx7SeriesPlatform):
         ),
 
         SPIResource(0,
-            cs="C1", clk="F1", copi="H1", cipo="G1",
+            cs_n="C1", clk="F1", copi="H1", cipo="G1",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 
@@ -49,7 +49,7 @@ class ArtyA7Platform(Xilinx7SeriesPlatform):
         ),
 
         *SPIFlashResources(0,
-            cs="L13", clk="L16", copi="K17", cipo="K18", wp="L14", hold="M14",
+            cs_n="L13", clk="L16", copi="K17", cipo="K18", wp_n="L14", hold_n="M14",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 
diff --git a/nmigen_boards/arty_s7.py b/nmigen_boards/arty_s7.py
index 633ba0a..4a40c02 100644
--- a/nmigen_boards/arty_s7.py
+++ b/nmigen_boards/arty_s7.py
@@ -34,7 +34,7 @@ class _ArtyS7Platform(Xilinx7SeriesPlatform):
         ),
 
         SPIResource(0,
-            cs="H16", clk="G16", copi="H17", cipo="K14",
+            cs_n="H16", clk="G16", copi="H17", cipo="K14",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 
@@ -44,7 +44,7 @@ class _ArtyS7Platform(Xilinx7SeriesPlatform):
         ),
 
         *SPIFlashResources(0,
-            cs="M13", clk="D11", copi="K17", cipo="K18", wp="L14", hold="M15",
+            cs_n="M13", clk="D11", copi="K17", cipo="K18", wp_n="L14", hold_n="M15",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 
diff --git a/nmigen_boards/atlys.py b/nmigen_boards/atlys.py
index 0f70ac6..ba2fbcb 100644
--- a/nmigen_boards/atlys.py
+++ b/nmigen_boards/atlys.py
@@ -71,7 +71,7 @@ class AtlysPlatform(XilinxSpartan6Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="AE14", clk="AH18", copi="AF14", cipo="AF20", wp="AG21", hold="AG17",
+            cs_n="AE14", clk="AH18", copi="AF14", cipo="AF20", wp_n="AG21", hold_n="AG17",
             attrs=Attrs(IOSTANDARD="LVCMOS25", SLEW="FAST"),
         ),
 
diff --git a/nmigen_boards/blackice.py b/nmigen_boards/blackice.py
index 5853fe4..70f1fef 100644
--- a/nmigen_boards/blackice.py
+++ b/nmigen_boards/blackice.py
@@ -34,7 +34,7 @@ class BlackIcePlatform(LatticeICE40Platform):
         ),
 
         SRAMResource(0,
-            cs="136", oe="45", we="120",
+            cs_n="136", oe_n="45", we_n="120",
             a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
             d="135 134 130 128 125 124 122 121 61 60 56 55 52 49 48 47",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
diff --git a/nmigen_boards/blackice_ii.py b/nmigen_boards/blackice_ii.py
index 2187d60..f05b063 100644
--- a/nmigen_boards/blackice_ii.py
+++ b/nmigen_boards/blackice_ii.py
@@ -35,10 +35,10 @@ class BlackIceIIPlatform(LatticeICE40Platform):
         ),
 
         SRAMResource(0,
-            cs="136", oe="29", we="120",
+            cs_n="136", oe_n="29", we_n="120",
             a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
             d="136 135 134 130 125 124 122 121 62 61 60 56 55 48 47 45",
-            dm="24 28",
+            dm_n="24 28",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
         ),
     ]
diff --git a/nmigen_boards/de0.py b/nmigen_boards/de0.py
index 5ba3e9a..e1c1f56 100644
--- a/nmigen_boards/de0.py
+++ b/nmigen_boards/de0.py
@@ -78,18 +78,18 @@ class DE0Platform(IntelPlatform):
         ),
 
         *SDCardResources(0,
-            clk="Y21", cmd="Y22", dat0="AA22", dat3="W21", wp="W20",
+            clk="Y21", cmd="Y22", dat0="AA22", dat3="W21", wp_n="W20",
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         SDRAMResource(0,
-            clk="E5", cke="E6", cs="G7", we="D6", ras="F7", cas="G8",
+            clk="E5", cke="E6", cs_n="G7", we_n="D6", ras_n="F7", cas_n="G8",
             ba="B5 A4", a="C4 A3 B3 C3 A5 C6 B6 A6 C7 B7 B4 A7 C8",
             dq="D10 G10 H10 E9 F9 G9 H9 F8 A8 B9 A9 C10 B10 A10 E10 F10", dqm="E7 B8",
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         *NORFlashResources(0,
-            rst="R1", byte="AA1",
-            cs="N8", oe="R6", we="P4", wp="T3", by="M7",
+            rst="R1", byte_n="AA1",
+            cs_n="N8", oe_n="R6", we_n="P4", wp_n="T3", by="M7",
             a="P7 P5 P6 N7 N5 N6 M8 M4 P2 N2 N1 M3 M2 M1 L7 L6 AA2 M5 M6 P1 P3 R2",
             dq="R7 P8 R8 U1 V2 V3 W1 Y1 T5 T7 T4 U2 V1 V4 W2 Y2",
             attrs=Attrs(io_standard="3.3-V LVTTL")),
diff --git a/nmigen_boards/de0_cv.py b/nmigen_boards/de0_cv.py
index 3d62c13..35788ad 100644
--- a/nmigen_boards/de0_cv.py
+++ b/nmigen_boards/de0_cv.py
@@ -77,7 +77,7 @@ class DE0CVPlatform(IntelPlatform):
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         SDRAMResource(0,
-            clk="AB11", cke="R6", cs="U6", we="AB5", ras="AB6", cas="V6",
+            clk="AB11", cke="R6", cs_n="U6", we_n="AB5", ras_n="AB6", cas_n="V6",
             ba="T7 AB7", a="W8 T8 U11 Y10 N6 AB10 P12 P7 P8 R5 U8 P6 R7",
             dq="Y9 T10 R9 Y11 R10 R11 R12 AA12 AA9 AB8 AA8 AA7 V10 V9 U10 T9", dqm="U12 N8",
             attrs=Attrs(io_standard="3.3-V LVCMOS")),
diff --git a/nmigen_boards/de10_lite.py b/nmigen_boards/de10_lite.py
index 21fd8a5..9f260ce 100644
--- a/nmigen_boards/de10_lite.py
+++ b/nmigen_boards/de10_lite.py
@@ -56,7 +56,7 @@ class DE10LitePlatform(IntelPlatform):
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         SDRAMResource(0,
-            clk="L14", cs="U20", we="V20", ras="U22", cas="U21",
+            clk="L14", cs_n="U20", we_n="V20", ras_n="U22", cas_n="U21",
             ba="T21 T22", a="U17 W19 V18 U18 U19 T18 T19 R18 P18 P19 T20 P20 R20",
             dq="Y21 Y20 AA22 AA21 Y22 W22 W20 V21 P21 J22 H21 H22 G22 G20 G19 F22",
             dqm="V22 J21", attrs=Attrs(io_standard="3.3-V LVCMOS")),
diff --git a/nmigen_boards/de10_nano.py b/nmigen_boards/de10_nano.py
index f8d7470..bf1fa73 100644
--- a/nmigen_boards/de10_nano.py
+++ b/nmigen_boards/de10_nano.py
@@ -40,7 +40,7 @@ class DE10NanoPlatform(IntelPlatform):
 
         # LTC2308 analogue-to-digital converter
         SPIResource(0,
-            cs="U9", clk="V10", copi="AC4", cipo="AD4",
+            cs_n="U9", clk="V10", copi="AC4", cipo="AD4",
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         # ADV7513 HDMI transmitter
diff --git a/nmigen_boards/ecp5_5g_evn.py b/nmigen_boards/ecp5_5g_evn.py
index 990a5f6..71d2e6f 100644
--- a/nmigen_boards/ecp5_5g_evn.py
+++ b/nmigen_boards/ecp5_5g_evn.py
@@ -70,7 +70,7 @@ class ECP55GEVNPlatform(LatticeECP5Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="R2", clk="U3", cipo="V2", copi="W2", wp="Y2", hold="W1",
+            cs_n="R2", clk="U3", cipo="V2", copi="W2", wp_n="Y2", hold_n="W1",
             attrs=Attrs(IO_TYPE="LVCMOS33")
         ),
 
diff --git a/nmigen_boards/ecpix5.py b/nmigen_boards/ecpix5.py
index 8f0bf7a..c4b6913 100644
--- a/nmigen_boards/ecpix5.py
+++ b/nmigen_boards/ecpix5.py
@@ -42,7 +42,7 @@ class _ECPIX5Platform(LatticeECP5Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="AA2", clk="AE3", cipo="AE2", copi="AD2", wp="AF2", hold="AE1",
+            cs_n="AA2", clk="AE3", cipo="AE2", copi="AD2", wp_n="AF2", hold_n="AE1",
             attrs=Attrs(IO_TYPE="LVCMOS33")
         ),
 
diff --git a/nmigen_boards/fomu_hacker.py b/nmigen_boards/fomu_hacker.py
index 8bb0025..95e7f61 100644
--- a/nmigen_boards/fomu_hacker.py
+++ b/nmigen_boards/fomu_hacker.py
@@ -28,7 +28,7 @@ class FomuHackerPlatform(LatticeICE40Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="C1", clk="D1", copi="F1", cipo="E1",
+            cs_n="C1", clk="D1", copi="F1", cipo="E1",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
         ),
     ]
diff --git a/nmigen_boards/fomu_pvt.py b/nmigen_boards/fomu_pvt.py
index 990442a..1303c0c 100644
--- a/nmigen_boards/fomu_pvt.py
+++ b/nmigen_boards/fomu_pvt.py
@@ -28,7 +28,7 @@ class FomuPVTPlatform(LatticeICE40Platform):
                 attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
 
         *SPIFlashResources(0,
-            cs="C1", clk="D1", copi="F1", cipo="E1",
+            cs_n="C1", clk="D1", copi="F1", cipo="E1",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
         ),
 
diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py
index 1c4ee54..bf8e98f 100644
--- a/nmigen_boards/genesys2.py
+++ b/nmigen_boards/genesys2.py
@@ -97,7 +97,7 @@ class Genesys2Platform(Xilinx7SeriesPlatform):
         Resource("audio_clk", 0,  # ADAU1761 MCLK
                  Pins("AK19", dir="o"), Attrs(IOSTANDARD="LVCMOS18")),
         SPIResource(0,  # OLED, SSD1306, 128 x 32
-                    cs="dummy-cs0", clk="AF17", copi="Y15",
+                    cs_n="dummy-cs0", clk="AF17", copi="Y15",
                     cipo="dummy-cipo0", reset="AB17",
                     attrs=Attrs(IOSTANDARD="LVCMOS18")),
         Resource("oled", 0,  # OLED, UG-2832HSWEG04
diff --git a/nmigen_boards/ice40_hx1k_blink_evn.py b/nmigen_boards/ice40_hx1k_blink_evn.py
index b2542cf..574f909 100644
--- a/nmigen_boards/ice40_hx1k_blink_evn.py
+++ b/nmigen_boards/ice40_hx1k_blink_evn.py
@@ -25,7 +25,7 @@ class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
         Resource("touch", 3, Pins("52"), Attrs(IO_STANDARD="SB_LVCMOS")),
 
         *SPIFlashResources(0,
-            cs="49", clk="48", copi="45", cipo="46",
+            cs_n="49", clk="48", copi="45", cipo="46",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")
         ),
     ]
diff --git a/nmigen_boards/ice40_hx8k_b_evn.py b/nmigen_boards/ice40_hx8k_b_evn.py
index 635cab4..d6d8729 100644
--- a/nmigen_boards/ice40_hx8k_b_evn.py
+++ b/nmigen_boards/ice40_hx8k_b_evn.py
@@ -29,7 +29,7 @@ class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="R12", clk="R11", copi="P12", cipo="P11",
+            cs_n="R12", clk="R11", copi="P12", cipo="P11",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")
         ),
     ]
diff --git a/nmigen_boards/ice40_up5k_b_evn.py b/nmigen_boards/ice40_up5k_b_evn.py
index d6254cb..3ac80af 100644
--- a/nmigen_boards/ice40_up5k_b_evn.py
+++ b/nmigen_boards/ice40_up5k_b_evn.py
@@ -38,7 +38,7 @@ class ICE40UP5KBEVNPlatform(LatticeICE40Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="16", clk="15", copi="14", cipo="17",
+            cs_n="16", clk="15", copi="14", cipo="17",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")
         ),
     ]
diff --git a/nmigen_boards/icebreaker.py b/nmigen_boards/icebreaker.py
index ecdfe1a..fc3302b 100644
--- a/nmigen_boards/icebreaker.py
+++ b/nmigen_boards/icebreaker.py
@@ -30,7 +30,7 @@ class ICEBreakerPlatform(LatticeICE40Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="16", clk="15", copi="14", cipo="17", wp="12", hold="13",
+            cs_n="16", clk="15", copi="14", cipo="17", wp_n="12", hold_n="13",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")
         ),
     ]
diff --git a/nmigen_boards/icebreaker_bitsy.py b/nmigen_boards/icebreaker_bitsy.py
index da5219d..b964c49 100644
--- a/nmigen_boards/icebreaker_bitsy.py
+++ b/nmigen_boards/icebreaker_bitsy.py
@@ -21,7 +21,7 @@ class ICEBreakerBitsyPlatform(LatticeICE40Platform):
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
 
         *SPIFlashResources(0,
-            cs="16", clk="15", copi="14", cipo="17", wp="18", hold="19",
+            cs_n="16", clk="15", copi="14", cipo="17", wp_n="18", hold_n="19",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")
         ),
 
diff --git a/nmigen_boards/icestick.py b/nmigen_boards/icestick.py
index 8104aff..c6c1a79 100644
--- a/nmigen_boards/icestick.py
+++ b/nmigen_boards/icestick.py
@@ -31,7 +31,7 @@ class ICEStickPlatform(LatticeICE40Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="71", clk="70", copi="67", cipo="68",
+            cs_n="71", clk="70", copi="67", cipo="68",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")
         ),
     ]
diff --git a/nmigen_boards/machxo3_sk.py b/nmigen_boards/machxo3_sk.py
index fcd769b..7ee1c68 100644
--- a/nmigen_boards/machxo3_sk.py
+++ b/nmigen_boards/machxo3_sk.py
@@ -36,7 +36,7 @@ class MachXO3SKPlatform(LatticeMachXO3LPlatform):
         ), # SW2
 
         *SPIFlashResources(0,
-            cs="R5", clk="P6", copi="T13", cipo="T6",
+            cs_n="R5", clk="P6", copi="T13", cipo="T6",
             attrs=Attrs(IO_TYPE="LVCMOS33")
         ),
     ]
diff --git a/nmigen_boards/mercury.py b/nmigen_boards/mercury.py
index 98b1f7b..6750921 100644
--- a/nmigen_boards/mercury.py
+++ b/nmigen_boards/mercury.py
@@ -40,19 +40,19 @@ class MercuryPlatform(XilinxSpartan3APlatform):
         # The serial interface and flash memory have a shared SPI bus.
         # FPGA is secondary.
         SPIResource("spi_serial", 0, role="peripheral",
-            cs="P39", clk="P53", copi="P46", cipo="P51",
+            cs_n="P39", clk="P53", copi="P46", cipo="P51",
             attrs=Attrs(IOSTANDARD="LVTTL"),
         ),
 
         # FPGA is primary.
         *SPIFlashResources(0,
-            cs="P27", clk="P53", copi="P46", cipo="P51",
+            cs_n="P27", clk="P53", copi="P46", cipo="P51",
             attrs=Attrs(IOSTANDARD="LVTTL")
         ),
 
         # ADC over SPI- FPGA is primary.
         SPIResource("spi_adc", 0, role="controller",
-            cs="P12", clk="P9", copi="P10", cipo="P21",
+            cs_n="P12", clk="P9", copi="P10", cipo="P21",
             attrs=Attrs(IOSTANDARD="LVTTL"),
         ),
 
@@ -101,7 +101,7 @@ class MercuryPlatform(XilinxSpartan3APlatform):
 
     sram = [
         SRAMResource(0,
-            cs="P3", we="gpio_0:29",
+            cs_n="P3", we_n="gpio_0:29",
             # According to the schematic, A19/Pin 25 on the SRAM is wired to
             # gpio-0:20. However, according to the SRAM's datasheet, pin 25 is
             # a NC. Do not expose for now.
diff --git a/nmigen_boards/mister.py b/nmigen_boards/mister.py
index 2eacedf..d961a3d 100644
--- a/nmigen_boards/mister.py
+++ b/nmigen_boards/mister.py
@@ -40,7 +40,7 @@ class MisterPlatform(IntelPlatform):
 
         # LTC2308 analogue-to-digital converter
         SPIResource(0,
-            cs="U9", clk="V10", copi="AC4", cipo="AD4",
+            cs_n="U9", clk="V10", copi="AC4", cipo="AD4",
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         # ADV7513 HDMI transmitter
@@ -65,7 +65,7 @@ class MisterPlatform(IntelPlatform):
         # MiSTer SDRAM Board (required)
         # https://github.com/MiSTer-devel/Hardware_MiSTer/blob/master/releases/sdram_xs_2.2.pdf
         SDRAMResource(0,
-            clk="20", cs="33", we="27", ras="32", cas="31",
+            clk="20", cs_n="33", we_n="27", ras_n="32", cas_n="31",
             ba="34 35", a="37 38 39 40 28 25 26 23 24 21 36 22 19",
             dq="1 2 3 4 5 6 7 8 18 17 16 15 14 13 9 10",
             dqm="", conn=("gpio", 0), attrs=Attrs(io_standard="3.3-V LVCMOS")),
diff --git a/nmigen_boards/nexys4ddr.py b/nmigen_boards/nexys4ddr.py
index d4da078..7219163 100644
--- a/nmigen_boards/nexys4ddr.py
+++ b/nmigen_boards/nexys4ddr.py
@@ -123,7 +123,7 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform):
             Attrs(IOSTANDARD="LVCMOS33")),
 
         *SPIFlashResources(0,
-            cs="L13", clk="E9", copi="K17", cipo="K18", wp="L14", hold="M14",
+            cs_n="L13", clk="E9", copi="K17", cipo="K18", wp_n="L14", hold_n="M14",
             attrs=Attrs(IOSTANDARD="LVCMOS33")),
 
         Resource("ddr2", 0,                                 # MT47H64M16HR-25:H
diff --git a/nmigen_boards/numato_mimas.py b/nmigen_boards/numato_mimas.py
index 2e7b78c..b43772f 100644
--- a/nmigen_boards/numato_mimas.py
+++ b/nmigen_boards/numato_mimas.py
@@ -24,7 +24,7 @@ class NumatoMimasPlatform(XilinxSpartan6Platform):
                          attrs=Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")),
 
         *SPIFlashResources(0,
-            cs="P38", clk="P70", copi="P64", cipo="65",
+            cs_n="P38", clk="P70", copi="P64", cipo="65",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
     ]
diff --git a/nmigen_boards/orangecrab_r0_1.py b/nmigen_boards/orangecrab_r0_1.py
index 0f91fdf..34a5c02 100644
--- a/nmigen_boards/orangecrab_r0_1.py
+++ b/nmigen_boards/orangecrab_r0_1.py
@@ -28,7 +28,7 @@ class OrangeCrabR0_1Platform(LatticeECP5Platform):
             attrs=Attrs(IO_TYPE="LVCMOS33")),
 
         *SPIFlashResources(0,
-            cs="U17", clk="U16", cipo="T18", copi="U18", wp="R18", hold="N18",
+            cs_n="U17", clk="U16", cipo="T18", copi="U18", wp_n="R18", hold_n="N18",
             attrs=Attrs(IO_TYPE="LVCMOS33"),
         ),
 
diff --git a/nmigen_boards/orangecrab_r0_2.py b/nmigen_boards/orangecrab_r0_2.py
index 6b6bc3d..10a3a77 100644
--- a/nmigen_boards/orangecrab_r0_2.py
+++ b/nmigen_boards/orangecrab_r0_2.py
@@ -32,7 +32,7 @@ class OrangeCrabR0_2Platform(LatticeECP5Platform):
             attrs=Attrs(IO_TYPE="SSTL135_I")),
 
         *SPIFlashResources(0,
-            cs="U17", clk="U16", cipo="T18", copi="U18", wp="R18", hold="N18",
+            cs_n="U17", clk="U16", cipo="T18", copi="U18", wp_n="R18", hold_n="N18",
             attrs=Attrs(IO_TYPE="LVCMOS33"),
         ),
 
diff --git a/nmigen_boards/quickfeather.py b/nmigen_boards/quickfeather.py
index f0a3e01..15ab157 100644
--- a/nmigen_boards/quickfeather.py
+++ b/nmigen_boards/quickfeather.py
@@ -33,10 +33,10 @@ class QuickfeatherPlatform(QuicklogicPlatform):
         ),
 
         SPIResource(0,
-            cs="11", clk="20", copi="16", cipo="17"
+            cs_n="11", clk="20", copi="16", cipo="17"
         ),
         SPIResource(1,
-            cs="37", clk="40", copi="36", cipo="42",
+            cs_n="37", clk="40", copi="36", cipo="42",
             role="peripheral"
         ),
 
diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py
index 8d5bd7e..0e0118a 100644
--- a/nmigen_boards/resources/interface.py
+++ b/nmigen_boards/resources/interface.py
@@ -56,21 +56,21 @@ def IrDAResource(number, *, rx, tx, en=None, sd=None,
     return Resource("irda", number, *io)
 
 
-def SPIResource(*args, cs, clk, copi, cipo, int=None, reset=None,
+def SPIResource(*args, cs_n, clk, copi, cipo, int=None, reset=None,
                 conn=None, attrs=None, role="controller"):
     assert role in ("controller", "peripheral")
     assert copi is not None or cipo is not None # support unidirectional SPI
 
     io = []
     if role == "controller":
-        io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn)))
+        io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn)))
         io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
         if copi is not None:
             io.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
         if cipo is not None:
             io.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
     else:  # peripheral
-        io.append(Subsignal("cs", PinsN(cs, dir="i", conn=conn, assert_width=1)))
+        io.append(Subsignal("cs", PinsN(cs_n, dir="i", conn=conn, assert_width=1)))
         io.append(Subsignal("clk", Pins(clk, dir="i", conn=conn, assert_width=1)))
         if copi is not None:
             io.append(Subsignal("copi", Pins(copi, dir="i", conn=conn, assert_width=1)))
diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py
index 064369f..a363068 100644
--- a/nmigen_boards/resources/memory.py
+++ b/nmigen_boards/resources/memory.py
@@ -7,22 +7,22 @@ __all__ = [
 ]
 
 
-def SPIFlashResources(*args, cs, clk, copi, cipo, wp=None, hold=None,
+def SPIFlashResources(*args, cs_n, clk, copi, cipo, wp_n=None, hold_n=None,
                       conn=None, attrs=None):
     resources = []
 
     io_all = []
     if attrs is not None:
         io_all.append(attrs)
-    io_all.append(Subsignal("cs",  PinsN(cs, dir="o", conn=conn)))
+    io_all.append(Subsignal("cs",  PinsN(cs_n, dir="o", conn=conn)))
     io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
 
     io_1x = list(io_all)
     io_1x.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
     io_1x.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
-    if wp is not None and hold is not None:
-        io_1x.append(Subsignal("wp",   PinsN(wp,   dir="o", conn=conn, assert_width=1)))
-        io_1x.append(Subsignal("hold", PinsN(hold, dir="o", conn=conn, assert_width=1)))
+    if wp_n is not None and hold_n is not None:
+        io_1x.append(Subsignal("wp",   PinsN(wp_n,   dir="o", conn=conn, assert_width=1)))
+        io_1x.append(Subsignal("hold", PinsN(hold_n, dir="o", conn=conn, assert_width=1)))
     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
                                      name_suffix="1x"))
 
@@ -32,9 +32,9 @@ def SPIFlashResources(*args, cs, clk, copi, cipo, wp=None, hold=None,
     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
                                      name_suffix="2x"))
 
-    if wp is not None and hold is not None:
+    if wp_n is not None and hold_n is not None:
         io_4x = list(io_all)
-        io_4x.append(Subsignal("dq", Pins(" ".join([copi, cipo, wp, hold]), dir="io", conn=conn,
+        io_4x.append(Subsignal("dq", Pins(" ".join([copi, cipo, wp_n, hold_n]), dir="io", conn=conn,
                                           assert_width=4)))
         resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
                                          name_suffix="4x"))
@@ -42,7 +42,7 @@ def SPIFlashResources(*args, cs, clk, copi, cipo, wp=None, hold=None,
     return resources
 
 
-def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=None, wp=None,
+def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=None, wp_n=None,
                     conn=None, attrs=None):
     resources = []
 
@@ -51,8 +51,8 @@ def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=N
         io_common.append(attrs)
     if cd is not None:
         io_common.append(Subsignal("cd", Pins(cd, dir="i", conn=conn, assert_width=1)))
-    if wp is not None:
-        io_common.append(Subsignal("wp", PinsN(wp, dir="i", conn=conn, assert_width=1)))
+    if wp_n is not None:
+        io_common.append(Subsignal("wp", PinsN(wp_n, dir="i", conn=conn, assert_width=1)))
 
     io_native = list(io_common)
     io_native.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
@@ -86,34 +86,34 @@ def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=N
     return resources
 
 
-def SRAMResource(*args, cs, oe=None, we, a, d, dm=None,
+def SRAMResource(*args, cs_n, oe_n=None, we_n, a, d, dm_n=None,
                  conn=None, attrs=None):
     io = []
-    io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1)))
-    if oe is not None:
+    io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+    if oe_n is not None:
         # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
-        io.append(Subsignal("oe", PinsN(oe, dir="o", conn=conn, assert_width=1)))
-    io.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1)))
+        io.append(Subsignal("oe", PinsN(oe_n, dir="o", conn=conn, assert_width=1)))
+    io.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
     io.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
     io.append(Subsignal("d", Pins(d, dir="io", conn=conn)))
-    if dm is not None:
-        io.append(Subsignal("dm", PinsN(dm, dir="o", conn=conn))) # dm="LB# UB#"
+    if dm_n is not None:
+        io.append(Subsignal("dm", PinsN(dm_n, dir="o", conn=conn))) # dm="LB# UB#"
     if attrs is not None:
         io.append(attrs)
     return Resource.family(*args, default_name="sram", ios=io)
 
 
-def SDRAMResource(*args, clk, cke=None, cs=None, we, ras, cas, ba, a, dq, dqm=None,
+def SDRAMResource(*args, clk, cke=None, cs_n=None, we_n, ras_n, cas_n, ba, a, dq, dqm=None,
                   conn=None, attrs=None):
     io = []
     io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
     if cke is not None:
         io.append(Subsignal("clk_en", Pins(cke, dir="o", conn=conn, assert_width=1)))
-    if cs is not None:
-        io.append(Subsignal("cs",  PinsN(cs,  dir="o", conn=conn, assert_width=1)))
-    io.append(Subsignal("we",  PinsN(we,  dir="o", conn=conn, assert_width=1)))
-    io.append(Subsignal("ras", PinsN(ras, dir="o", conn=conn, assert_width=1)))
-    io.append(Subsignal("cas", PinsN(cas, dir="o", conn=conn, assert_width=1)))
+    if cs_n is not None:
+        io.append(Subsignal("cs", PinsN(cs_n,  dir="o", conn=conn, assert_width=1)))
+    io.append(Subsignal("we",  PinsN(we_n,  dir="o", conn=conn, assert_width=1)))
+    io.append(Subsignal("ras", PinsN(ras_n, dir="o", conn=conn, assert_width=1)))
+    io.append(Subsignal("cas", PinsN(cas_n, dir="o", conn=conn, assert_width=1)))
     io.append(Subsignal("ba", Pins(ba, dir="o", conn=conn)))
     io.append(Subsignal("a",  Pins(a,  dir="o", conn=conn)))
     io.append(Subsignal("dq", Pins(dq, dir="io", conn=conn)))
@@ -124,20 +124,20 @@ def SDRAMResource(*args, clk, cke=None, cs=None, we, ras, cas, ba, a, dq, dqm=No
     return Resource.family(*args, default_name="sdram", ios=io)
 
 
-def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq,
+def NORFlashResources(*args, rst=None, byte_n=None, cs_n, oe_n, we_n, wp_n, by, a, dq,
                       conn=None, attrs=None):
     resources = []
 
     io_common = []
     if rst is not None:
         io_common.append(Subsignal("rst", Pins(rst, dir="o", conn=conn, assert_width=1)))
-    io_common.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1)))
-    io_common.append(Subsignal("oe", PinsN(oe, dir="o", conn=conn, assert_width=1)))
-    io_common.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1)))
-    io_common.append(Subsignal("wp", PinsN(wp, dir="o", conn=conn, assert_width=1)))
+    io_common.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+    io_common.append(Subsignal("oe", PinsN(oe_n, dir="o", conn=conn, assert_width=1)))
+    io_common.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
+    io_common.append(Subsignal("wp", PinsN(wp_n, dir="o", conn=conn, assert_width=1)))
     io_common.append(Subsignal("rdy", Pins(by, dir="i", conn=conn, assert_width=1)))
 
-    if byte is None:
+    if byte_n is None:
         io_8bit = list(io_common)
         io_8bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
         io_8bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=8)))
@@ -147,7 +147,7 @@ def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq,
         *dq_0_14, dq15_am1 = dq.split()
 
         # If present in a requested resource, this pin needs to be strapped correctly.
-        io_common.append(Subsignal("byte", PinsN(byte, dir="o", conn=conn, assert_width=1)))
+        io_common.append(Subsignal("byte", PinsN(byte_n, dir="o", conn=conn, assert_width=1)))
 
         io_8bit = list(io_common)
         io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o", conn=conn)))
diff --git a/nmigen_boards/rz_easyfpga_a2_2.py b/nmigen_boards/rz_easyfpga_a2_2.py
index b6ae585..3f6ee08 100644
--- a/nmigen_boards/rz_easyfpga_a2_2.py
+++ b/nmigen_boards/rz_easyfpga_a2_2.py
@@ -35,7 +35,7 @@ class RZEasyFPGAA2_2Platform(IntelPlatform):
 
         # Connections to the SKHynix RAM chip on board.
         SDRAMResource(0,
-            clk="43", cs="72", we="69", ras="71", cas="70",
+            clk="43", cs_n="72", we_n="69", ras_n="71", cas_n="70",
             ba="73 74", a="76 77 80 83 68 67 66 65 64 60 75 59",
             dq="28 30 31 32 33 34 38 39 54 53 52 51 50 49 46 44",
             dqm="42 55", attrs=Attrs(io_standard="3.3-V LVCMOS")),
diff --git a/nmigen_boards/sk_xc6slx9.py b/nmigen_boards/sk_xc6slx9.py
index d9acdc2..8a84c9e 100644
--- a/nmigen_boards/sk_xc6slx9.py
+++ b/nmigen_boards/sk_xc6slx9.py
@@ -20,12 +20,12 @@ class SK_XC6SLX9Platform(XilinxSpartan6Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="P38", clk="P70", copi="P64", cipo="65",
+            cs_n="P38", clk="P70", copi="P64", cipo="65",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 
         SRAMResource(0,
-            cs="P97", oe="P45", we="P51",
+            cs_n="P97", oe_n="P45", we_n="P51",
             a="P39 P40 P41 P43 P44 P55 P56 P57 P58 P59 P82 P81 P80 P79 P78 P66 P62 P61 P60",
             d="P46 P47 P48 P50 P75 P74 P69 P67",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
diff --git a/nmigen_boards/supercon19badge.py b/nmigen_boards/supercon19badge.py
index cba9465..f670991 100644
--- a/nmigen_boards/supercon19badge.py
+++ b/nmigen_boards/supercon19badge.py
@@ -125,7 +125,7 @@ class Supercon19BadgePlatform(LatticeECP5Platform):
             Attrs(IO_TYPE="LVCMOS33", SLEWRATE="SLOW")
         ),
 
-        SDRAMResource(0, clk="D11", cke="C11", cs="C7", we="B6", ras="D6", cas="A6",
+        SDRAMResource(0, clk="D11", cke="C11", cs_n="C7", we_n="B6", ras_n="D6", cas_n="A6",
             ba="A7 C8", a="A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11",
             dq="C5 B5 A5 C6 B10 C10 D10 A9", dqm="A10",
             attrs=Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")
diff --git a/nmigen_boards/te0714_03_50_2I.py b/nmigen_boards/te0714_03_50_2I.py
index 67da63e..7c84fde 100644
--- a/nmigen_boards/te0714_03_50_2I.py
+++ b/nmigen_boards/te0714_03_50_2I.py
@@ -15,7 +15,7 @@ class TE0714_03_50_2IPlatform(Xilinx7SeriesPlatform):
         Resource("clk25", 0, Pins("T14", dir="i"), Clock(25e6), Attrs(IOSTANDARD="LVCMOS18")),
         *LEDResources(pins="K18", attrs=Attrs(IOSTANDARD="LVCMOS18")),
         *SPIFlashResources(0,
-            cs="L15", clk="E8", copi="K16", cipo="K17", wp="J15", hold="J16",
+            cs_n="L15", clk="E8", copi="K16", cipo="K17", wp_n="J15", hold_n="J16",
             attrs=Attrs(IOSTANDARD="LVCMOS18")
         )
     ]
diff --git a/nmigen_boards/tinyfpga_bx.py b/nmigen_boards/tinyfpga_bx.py
index f7673be..e862d42 100644
--- a/nmigen_boards/tinyfpga_bx.py
+++ b/nmigen_boards/tinyfpga_bx.py
@@ -24,7 +24,7 @@ class TinyFPGABXPlatform(LatticeICE40Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="F7", clk="G7", copi="G6", cipo="H7", wp="H4", hold="J8",
+            cs_n="F7", clk="G7", copi="G6", cipo="H7", wp_n="H4", hold_n="J8",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")
         ),
     ]
diff --git a/nmigen_boards/ulx3s.py b/nmigen_boards/ulx3s.py
index 5f9c924..1970106 100644
--- a/nmigen_boards/ulx3s.py
+++ b/nmigen_boards/ulx3s.py
@@ -66,14 +66,14 @@ class _ULX3SPlatform(LatticeECP5Platform):
         ),
 
         SDRAMResource(0,
-            clk="F19", cke="F20", cs="P20", we="T20", cas="T19", ras="R20", dqm="U19 E20",
+            clk="F19", cke="F20", cs_n="P20", we_n="T20", cas_n="T19", ras_n="R20", dqm="U19 E20",
             ba="P19 N20", a="M20 M19 L20 L19 K20 K19 K18 J20 J19 H20 N19 G20 G19",
             dq="J16 L18 M18 N18 P18 T18 T17 U20 E19 D20 D19 C20 E18 F18 J18 J17",
             attrs=Attrs(PULLMODE="NONE", DRIVE="4", SLEWRATE="FAST", IO_TYPE="LVCMOS33")
         ),
 
         # SPI bus for ADC.
-        SPIResource("adc", cs="R17", copi="R16", cipo="U16", clk="P17",
+        SPIResource("adc", cs_n="R17", copi="R16", cipo="U16", clk="P17",
             attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")),
 
         # TRRS audio jack
diff --git a/nmigen_boards/upduino_v1.py b/nmigen_boards/upduino_v1.py
index 6f5a0d6..a24a7a7 100644
--- a/nmigen_boards/upduino_v1.py
+++ b/nmigen_boards/upduino_v1.py
@@ -22,7 +22,7 @@ class UpduinoV1Platform(LatticeICE40Platform):
                  Attrs(IO_STANDARD="SB_LVCMOS")),
 
         *SPIFlashResources(0,
-            cs="16", clk="15", cipo="17", copi="14",
+            cs_n="16", clk="15", cipo="17", copi="14",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS")
         ),
     ]
diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py
index 8a6eb81..1a5870a 100644
--- a/nmigen_boards/versa_ecp5.py
+++ b/nmigen_boards/versa_ecp5.py
@@ -55,7 +55,7 @@ class VersaECP5Platform(LatticeECP5Platform):
         ),
 
         *SPIFlashResources(0,
-            cs="R2", clk="U3", cipo="W2", copi="V2", wp="Y2", hold="W1",
+            cs_n="R2", clk="U3", cipo="W2", copi="V2", wp_n="Y2", hold_n="W1",
             attrs=Attrs(IO_TYPE="LVCMOS33")
         ),