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-rw-r--r--nmigen_boards/de0.py14
-rw-r--r--nmigen_boards/de0_cv.py14
-rw-r--r--nmigen_boards/de10_lite.py13
-rw-r--r--nmigen_boards/genesys2.py14
-rw-r--r--nmigen_boards/mercury.py15
-rw-r--r--nmigen_boards/mister.py14
-rw-r--r--nmigen_boards/nexys4ddr.py13
-rw-r--r--nmigen_boards/resources/display.py17
-rw-r--r--nmigen_boards/rz_easyfpga_a2_2.py10
9 files changed, 62 insertions, 62 deletions
diff --git a/nmigen_boards/de0.py b/nmigen_boards/de0.py
index e1c1f56..0285499 100644
--- a/nmigen_boards/de0.py
+++ b/nmigen_boards/de0.py
@@ -57,14 +57,12 @@ class DE0Platform(IntelPlatform):
Attrs(io_standard="3.3-V LVTTL")
),
- Resource("vga", 0,
- Subsignal("r", Pins("H19 H17 H20 H21", dir="o")),
- Subsignal("g", Pins("H22 J17 K17 J21", dir="o")),
- Subsignal("b", Pins("K22 K21 J22 K18", dir="o")),
- Subsignal("hs", Pins("L21", dir="o")),
- Subsignal("vs", Pins("L22", dir="o")),
- Attrs(io_standard="3.3-V LVTTL")
- ),
+ VGAResource(0,
+ r="H19 H17 H20 H21",
+ g="H22 J17 K17 J21",
+ b="K22 K21 J22 K18",
+ hs="L21", vs="L22",
+ attrs=Attrs(io_standard="3.3-V LVTTL")),
Resource("ps2_host", 0, # Keyboard
Subsignal("clk", Pins("P22", dir="i")),
diff --git a/nmigen_boards/de0_cv.py b/nmigen_boards/de0_cv.py
index 35788ad..4abbe88 100644
--- a/nmigen_boards/de0_cv.py
+++ b/nmigen_boards/de0_cv.py
@@ -52,14 +52,12 @@ class DE0CVPlatform(IntelPlatform):
a="N9", b="M8", c="T14", d="P14", e="C1", f="C2", g="W19", invert=True,
attrs=Attrs(io_standard="3.3-V LVTTL")),
- Resource("vga", 0,
- Subsignal("r", Pins("A9 B10 C9 A5", dir="o")),
- Subsignal("g", Pins("L7 K7 J7 J8", dir="o")),
- Subsignal("b", Pins("B6 B7 A8 A7", dir="o")),
- Subsignal("hs", Pins("H8", dir="o")),
- Subsignal("vs", Pins("G8", dir="o")),
- Attrs(io_standard="3.3-V LVTTL")
- ),
+ VGAResource(0,
+ r="A9 B10 C9 A5",
+ g="L7 K7 J7 J8",
+ b="B6 B7 A8 A7",
+ hs="H8", vs="G8",
+ attrs=Attrs(io_standard="3.3-V LVTTL")),
Resource("ps2_host", 0, # Keyboard
Subsignal("clk", Pins("D3", dir="i")),
diff --git a/nmigen_boards/de10_lite.py b/nmigen_boards/de10_lite.py
index 9f260ce..21b7d09 100644
--- a/nmigen_boards/de10_lite.py
+++ b/nmigen_boards/de10_lite.py
@@ -61,13 +61,12 @@ class DE10LitePlatform(IntelPlatform):
dq="Y21 Y20 AA22 AA21 Y22 W22 W20 V21 P21 J22 H21 H22 G22 G20 G19 F22",
dqm="V22 J21", attrs=Attrs(io_standard="3.3-V LVCMOS")),
- Resource("vga", 0,
- Subsignal("r", Pins("AA1 V1 Y2 Y1", dir="o")),
- Subsignal("g", Pins("W1 T2 R2 R1", dir="o")),
- Subsignal("b", Pins("P1 T1 P4 N2", dir="o")),
- Subsignal("hs", Pins("N3", dir="o")),
- Subsignal("vs", Pins("N1", dir="o")),
- Attrs(io_standard="3.3-V LVTTL"))
+ VGAResource(0,
+ r="AA1 V1 Y2 Y1",
+ g="W1 T2 R2 R1",
+ b="P1 T1 P4 N2",
+ hs="N3", vs="N1",
+ attrs=Attrs(io_standard="3.3-V LVTTL"))
]
connectors = [
Connector("gpio", 0,
diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py
index bf8e98f..0a2aef7 100644
--- a/nmigen_boards/genesys2.py
+++ b/nmigen_boards/genesys2.py
@@ -127,14 +127,12 @@ class Genesys2Platform(Xilinx7SeriesPlatform):
DiffPairs(p="AJ26 AG27 AH26",
n="AK26 AG28 AH27", dir="i")),
Attrs(IOSTANDARD="TMDS_33")),
- Resource("vga", 0,
- Subsignal("r", Pins("AK25 AG25 AH25 AK24 AJ24", dir="o")),
- Subsignal("g", Pins("AJ23 AJ22 AH22 AK21 AJ21 AK23",
- dir="o")),
- Subsignal("b", Pins("AH20 AG20 AF21 AK20 AG22", dir="o")),
- Subsignal("hsync", PinsN("AF20", dir="o")),
- Subsignal("vsync", PinsN("AG23", dir="o")),
- Attrs(IOSTANDARD="LVCMOS33")),
+ VGAResource(0,
+ r="AK25 AG25 AH25 AK24 AJ24",
+ g="AJ23 AJ22 AH22 AK21 AJ21 AK23",
+ b="AH20 AG20 AF21 AK20 AG22",
+ hs="AF20", vs="AG23", invert_sync=True,
+ attrs=Attrs(IOSTANDARD="LVCMOS33")),
*SDCardResources(0, clk="R28", cmd="R29", dat0="R26", dat1="R30",
dat2="P29", dat3="T30", cd="P28",
attrs=Attrs(IOSTANDARD="LVCMOS33")),
diff --git a/nmigen_boards/mercury.py b/nmigen_boards/mercury.py
index 6750921..b03bb88 100644
--- a/nmigen_boards/mercury.py
+++ b/nmigen_boards/mercury.py
@@ -159,15 +159,12 @@ class MercuryPlatform(XilinxSpartan3APlatform):
]
_vga = [
- Resource("vga_out", 0,
- Subsignal("hsync", PinsN("led_0:3", dir="o")),
- Subsignal("vsync", PinsN("led_0:4", dir="o")),
-
- Subsignal("r", Pins("dio_0:1 dio_0:2 dio_0:3", dir="o")),
- Subsignal("g", Pins("dio_0:4 dio_0:5 dio_0:6", dir="o")),
- Subsignal("b", Pins("dio_0:7 clkio_0:1", dir="o")),
- Attrs(IOSTANDARD="LVCMOS33", SLEW="FAST")
- )
+ VGAResource(0,
+ r="dio_0:1 dio_0:2 dio_0:3",
+ g="dio_0:4 dio_0:5 dio_0:6",
+ b="dio_0:7 clkio_0:1",
+ hs="led_0:3", vs="led_0:4", invert_sync=True,
+ Attrs(IOSTANDARD="LVCMOS33", SLEW="FAST"))
]
_extclk = [
diff --git a/nmigen_boards/mister.py b/nmigen_boards/mister.py
index d961a3d..9d08cff 100644
--- a/nmigen_boards/mister.py
+++ b/nmigen_boards/mister.py
@@ -93,13 +93,13 @@ class MisterPlatform(IntelPlatform):
conn=("gpio", 1), attrs=Attrs(io_standard="3.3-V LVTTL")),
# The schematic is difficult to understand here...
- Resource("vga", 0,
- Subsignal("r", Pins("28 32 34 36 38 40", dir="o", conn=("gpio", 1))),
- Subsignal("g", Pins("27 31 33 35 37 39", dir="o", conn=("gpio", 1))),
- Subsignal("b", Pins("21 23 25 26 24 24", dir="o", conn=("gpio", 1))),
- Subsignal("hs", Pins("20", dir="o", conn=("gpio", 1))),
- Subsignal("vs", Pins("19", dir="o", conn=("gpio", 1))),
- Attrs(io_standard="3.3-V LVTTL"))
+ VGAResource(0,
+ r="28 32 34 36 38 40",
+ g="27 31 33 35 37 39",
+ b="21 23 25 26 24 24",
+ hs="20", vs="19",
+ conn=("gpio", 1),
+ attrs=Attrs(io_standard="3.3-V LVTTL"))
]
connectors = [
# Located on the top of the board, above the chip.
diff --git a/nmigen_boards/nexys4ddr.py b/nmigen_boards/nexys4ddr.py
index 7219163..1e32653 100644
--- a/nmigen_boards/nexys4ddr.py
+++ b/nmigen_boards/nexys4ddr.py
@@ -57,13 +57,12 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform):
Resource("button_down", 0,
Pins("P18", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
- Resource("vga", 0,
- Subsignal("r", Pins("A3 B4 C5 A4", dir="o")),
- Subsignal("g", Pins("C6 A5 B6 A6", dir="o")),
- Subsignal("b", Pins("B7 C7 D7 D8", dir="o")),
- Subsignal("hs", Pins("B11" , dir="o")),
- Subsignal("vs", Pins("B12" , dir="o")),
- Attrs(IOSTANDARD="LVCMOS33")),
+ VGAResource(0,
+ r="A3 B4 C5 A4",
+ g="C6 A5 B6 A6",
+ b="B7 C7 D7 D8",
+ hs="B11", vs="B12",
+ attrs=Attrs(IOSTANDARD="LVCMOS33")),
*SDCardResources(0,
clk="B1", cmd="C1", cd="A1",
diff --git a/nmigen_boards/resources/display.py b/nmigen_boards/resources/display.py
index f145119..4255db8 100644
--- a/nmigen_boards/resources/display.py
+++ b/nmigen_boards/resources/display.py
@@ -1,7 +1,7 @@
from nmigen.build import *
-__all__ = ["Display7SegResource"]
+__all__ = ["Display7SegResource", "VGAResource"]
def Display7SegResource(*args, a, b, c, d, e, f, g, dp=None, invert=False,
@@ -19,3 +19,18 @@ def Display7SegResource(*args, a, b, c, d, e, f, g, dp=None, invert=False,
if attrs is not None:
ios.append(attrs)
return Resource.family(*args, default_name="display_7seg", ios=ios)
+
+
+def VGAResource(*args, r, g, b, vs, hs, invert_sync=False, conn=None, attrs=None):
+ ios = []
+
+ ios.append(Subsignal("r", Pins(r, dir="o", conn=conn)))
+ ios.append(Subsignal("g", Pins(g, dir="o", conn=conn)))
+ ios.append(Subsignal("b", Pins(b, dir="o", conn=conn)))
+ ios.append(Subsignal("hs", Pins(hs, dir="o", invert=invert_sync, conn=conn, assert_width=1)))
+ ios.append(Subsignal("vs", Pins(vs, dir="o", invert=invert_sync, conn=conn, assert_width=1)))
+
+ if attrs is not None:
+ ios.append(attrs)
+
+ return Resource.family(*args, default_name="vga", ios=ios)
diff --git a/nmigen_boards/rz_easyfpga_a2_2.py b/nmigen_boards/rz_easyfpga_a2_2.py
index 3f6ee08..892b546 100644
--- a/nmigen_boards/rz_easyfpga_a2_2.py
+++ b/nmigen_boards/rz_easyfpga_a2_2.py
@@ -41,13 +41,9 @@ class RZEasyFPGAA2_2Platform(IntelPlatform):
dqm="42 55", attrs=Attrs(io_standard="3.3-V LVCMOS")),
# VGA connector, located on the right of the board.
- Resource("vga", 0,
- Subsignal("r", Pins("106", dir="o")),
- Subsignal("g", Pins("105", dir="o")),
- Subsignal("b", Pins("104", dir="o")),
- Subsignal("hs", Pins("101", dir="o")),
- Subsignal("vs", Pins("103", dir="o")),
- ),
+ VGAResource(0,
+ r="106", g="105", b="104",
+ hs="101", vs="103"),
# 4 digit 7 segment display, located on top of the board.
Display7SegResource(0,
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-26 18:43:42 +0000