diff options
| -rw-r--r-- | nmigen_boards/genesys2.py | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py index a82ceaa..40dbced 100644 --- a/nmigen_boards/genesys2.py +++ b/nmigen_boards/genesys2.py @@ -142,15 +142,9 @@ class Genesys2Platform(Xilinx7SeriesPlatform): attrs=Attrs(IOSTANDARD="LVCMOS33")), Resource("sd_card_rst", 0, Pins("AE24", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - Resource("ulpi", 0, - Subsignal("rst", PinsN("AB14", dir="o")), - Subsignal("clk", Pins("AD18", dir="i")), - Subsignal("d", Pins("AE14 AE15 AC15 AC16 " - "AB15 AA15 AD14 AC14", dir="io")), - Subsignal("dir", Pins("Y16", dir="i")), - Subsignal("stp", Pins("AA17", dir="o")), - Subsignal("nxt", Pins("AA16", dir="i")), - Attrs(IOSTANDARD="LVCMOS18")), + ULPIResource(0, data="AE14 AE15 AC15 AC16 AB15 AA15 AD14 AC14", + rst="AB14", clk="AD18", dir="Y16", stp="AA17", nxt="AA16", + clk_dir="i", rst_invert=True, attrs=Attrs(IOSTANDARD="LVCMOS18")), Resource("vusb_oc", 0, PinsN("AF16", dir="i"), Attrs(IOSTANDARD="LVCMOS18")), Resource("eth_rgmii", 0, |