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-rw-r--r--amaranth_boards/resources/__init__.py4
-rw-r--r--amaranth_boards/resources/display.py36
-rw-r--r--amaranth_boards/resources/interface.py144
-rw-r--r--amaranth_boards/resources/memory.py190
-rw-r--r--amaranth_boards/resources/user.py43
5 files changed, 417 insertions, 0 deletions
diff --git a/amaranth_boards/resources/__init__.py b/amaranth_boards/resources/__init__.py
new file mode 100644
index 0000000..531eb5e
--- /dev/null
+++ b/amaranth_boards/resources/__init__.py
@@ -0,0 +1,4 @@
+from .display import *
+from .interface import *
+from .memory import *
+from .user import *
diff --git a/amaranth_boards/resources/display.py b/amaranth_boards/resources/display.py
new file mode 100644
index 0000000..cf245e8
--- /dev/null
+++ b/amaranth_boards/resources/display.py
@@ -0,0 +1,36 @@
+from amaranth.build import *
+
+
+__all__ = ["Display7SegResource", "VGAResource"]
+
+
+def Display7SegResource(*args, a, b, c, d, e, f, g, dp=None, invert=False,
+ conn=None, attrs=None):
+ ios = []
+ ios.append(Subsignal("a", Pins(a, dir="o", invert=invert, conn=conn, assert_width=1)))
+ ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, conn=conn, assert_width=1)))
+ ios.append(Subsignal("c", Pins(c, dir="o", invert=invert, conn=conn, assert_width=1)))
+ ios.append(Subsignal("d", Pins(d, dir="o", invert=invert, conn=conn, assert_width=1)))
+ ios.append(Subsignal("e", Pins(e, dir="o", invert=invert, conn=conn, assert_width=1)))
+ ios.append(Subsignal("f", Pins(f, dir="o", invert=invert, conn=conn, assert_width=1)))
+ ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, conn=conn, assert_width=1)))
+ if dp is not None:
+ ios.append(Subsignal("dp", Pins(dp, dir="o", invert=invert, conn=conn, assert_width=1)))
+ if attrs is not None:
+ ios.append(attrs)
+ return Resource.family(*args, default_name="display_7seg", ios=ios)
+
+
+def VGAResource(*args, r, g, b, vs, hs, invert_sync=False, conn=None, attrs=None):
+ ios = []
+
+ ios.append(Subsignal("r", Pins(r, dir="o", conn=conn)))
+ ios.append(Subsignal("g", Pins(g, dir="o", conn=conn)))
+ ios.append(Subsignal("b", Pins(b, dir="o", conn=conn)))
+ ios.append(Subsignal("hs", Pins(hs, dir="o", invert=invert_sync, conn=conn, assert_width=1)))
+ ios.append(Subsignal("vs", Pins(vs, dir="o", invert=invert_sync, conn=conn, assert_width=1)))
+
+ if attrs is not None:
+ ios.append(attrs)
+
+ return Resource.family(*args, default_name="vga", ios=ios)
diff --git a/amaranth_boards/resources/interface.py b/amaranth_boards/resources/interface.py
new file mode 100644
index 0000000..8941be1
--- /dev/null
+++ b/amaranth_boards/resources/interface.py
@@ -0,0 +1,144 @@
+from amaranth.build import *
+
+
+__all__ = [
+ "UARTResource", "IrDAResource", "SPIResource", "I2CResource",
+ "DirectUSBResource", "ULPIResource", "PS2Resource",
+]
+
+
+def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
+ conn=None, attrs=None, role=None):
+ if any(line is not None for line in (rts, cts, dtr, dsr, dcd, ri)):
+ assert role in ("dce", "dte")
+ if role == "dte":
+ dce_to_dte = "i"
+ dte_to_dce = "o"
+ else:
+ dce_to_dte = "o"
+ dte_to_dce = "i"
+
+ io = []
+ io.append(Subsignal("rx", Pins(rx, dir="i", conn=conn, assert_width=1)))
+ io.append(Subsignal("tx", Pins(tx, dir="o", conn=conn, assert_width=1)))
+ if rts is not None:
+ io.append(Subsignal("rts", Pins(rts, dir=dte_to_dce, conn=conn, assert_width=1)))
+ if cts is not None:
+ io.append(Subsignal("cts", Pins(cts, dir=dce_to_dte, conn=conn, assert_width=1)))
+ if dtr is not None:
+ io.append(Subsignal("dtr", Pins(dtr, dir=dte_to_dce, conn=conn, assert_width=1)))
+ if dsr is not None:
+ io.append(Subsignal("dsr", Pins(dsr, dir=dce_to_dte, conn=conn, assert_width=1)))
+ if dcd is not None:
+ io.append(Subsignal("dcd", Pins(dcd, dir=dce_to_dte, conn=conn, assert_width=1)))
+ if ri is not None:
+ io.append(Subsignal("ri", Pins(ri, dir=dce_to_dte, conn=conn, assert_width=1)))
+ if attrs is not None:
+ io.append(attrs)
+ return Resource.family(*args, default_name="uart", ios=io)
+
+
+def IrDAResource(number, *, rx, tx, en=None, sd=None,
+ conn=None, attrs=None):
+ # Exactly one of en (active-high enable) or sd (shutdown, active-low enable) should
+ # be specified, and it is mapped to a logic level en subsignal.
+ assert (en is not None) ^ (sd is not None)
+
+ io = []
+ io.append(Subsignal("rx", Pins(rx, dir="i", conn=conn, assert_width=1)))
+ io.append(Subsignal("tx", Pins(tx, dir="o", conn=conn, assert_width=1)))
+ if en is not None:
+ io.append(Subsignal("en", Pins(en, dir="o", conn=conn, assert_width=1)))
+ if sd is not None:
+ io.append(Subsignal("en", PinsN(sd, dir="o", conn=conn, assert_width=1)))
+ if attrs is not None:
+ io.append(attrs)
+ return Resource("irda", number, *io)
+
+
+def SPIResource(*args, cs_n, clk, copi, cipo, int=None, reset=None,
+ conn=None, attrs=None, role="controller"):
+ assert role in ("controller", "peripheral")
+ assert copi is not None or cipo is not None # support unidirectional SPI
+
+ io = []
+ if role == "controller":
+ io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn)))
+ io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
+ if copi is not None:
+ io.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
+ if cipo is not None:
+ io.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
+ else: # peripheral
+ io.append(Subsignal("cs", PinsN(cs_n, dir="i", conn=conn, assert_width=1)))
+ io.append(Subsignal("clk", Pins(clk, dir="i", conn=conn, assert_width=1)))
+ if copi is not None:
+ io.append(Subsignal("copi", Pins(copi, dir="i", conn=conn, assert_width=1)))
+ if cipo is not None:
+ io.append(Subsignal("cipo", Pins(cipo, dir="oe", conn=conn, assert_width=1)))
+ if int is not None:
+ if role == "controller":
+ io.append(Subsignal("int", Pins(int, dir="i", conn=conn)))
+ else:
+ io.append(Subsignal("int", Pins(int, dir="oe", conn=conn, assert_width=1)))
+ if reset is not None:
+ if role == "controller":
+ io.append(Subsignal("reset", Pins(reset, dir="o", conn=conn)))
+ else:
+ io.append(Subsignal("reset", Pins(reset, dir="i", conn=conn, assert_width=1)))
+ if attrs is not None:
+ io.append(attrs)
+ return Resource.family(*args, default_name="spi", ios=io)
+
+
+def I2CResource(*args, scl, sda, conn=None, attrs=None):
+ io = []
+ io.append(Subsignal("scl", Pins(scl, dir="io", conn=conn, assert_width=1)))
+ io.append(Subsignal("sda", Pins(sda, dir="io", conn=conn, assert_width=1)))
+ if attrs is not None:
+ io.append(attrs)
+ return Resource.family(*args, default_name="i2c", ios=io)
+
+
+def DirectUSBResource(*args, d_p, d_n, pullup=None, vbus_valid=None, conn=None, attrs=None):
+
+ io = []
+ io.append(Subsignal("d_p", Pins(d_p, dir="io", conn=conn, assert_width=1)))
+ io.append(Subsignal("d_n", Pins(d_n, dir="io", conn=conn, assert_width=1)))
+ if pullup:
+ io.append(Subsignal("pullup", Pins(pullup, dir="o", conn=conn, assert_width=1)))
+ if vbus_valid:
+ io.append(Subsignal("vbus_valid", Pins(vbus_valid, dir="i", conn=conn, assert_width=1)))
+ if attrs is not None:
+ io.append(attrs)
+ return Resource.family(*args, default_name="usb", ios=io)
+
+
+def ULPIResource(*args, data, clk, dir, nxt, stp, rst=None,
+ clk_dir='i', rst_invert=False, attrs=None, conn=None):
+ assert clk_dir in ('i', 'o',)
+
+ io = []
+ io.append(Subsignal("data", Pins(data, dir="io", conn=conn, assert_width=8)))
+ io.append(Subsignal("clk", Pins(clk, dir=clk_dir, conn=conn, assert_width=1)))
+ io.append(Subsignal("dir", Pins(dir, dir="i", conn=conn, assert_width=1)))
+ io.append(Subsignal("nxt", Pins(nxt, dir="i", conn=conn, assert_width=1)))
+ io.append(Subsignal("stp", Pins(stp, dir="o", conn=conn, assert_width=1)))
+ if rst is not None:
+ io.append(Subsignal("rst", Pins(rst, dir="o", invert=rst_invert,
+ conn=conn, assert_width=1)))
+ if attrs is not None:
+ io.append(attrs)
+ return Resource.family(*args, default_name="usb", ios=io)
+
+
+def PS2Resource(*args, clk, dat, conn=None, attrs=None):
+ ios = []
+
+ ios.append(Subsignal("clk", Pins(clk, dir="i", conn=conn, assert_width=1))),
+ ios.append(Subsignal("dat", Pins(dat, dir="io", conn=conn, assert_width=1))),
+
+ if attrs is not None:
+ ios.append(attrs)
+
+ return Resource.family(*args, default_name="ps2", ios=ios)
diff --git a/amaranth_boards/resources/memory.py b/amaranth_boards/resources/memory.py
new file mode 100644
index 0000000..65eb5d5
--- /dev/null
+++ b/amaranth_boards/resources/memory.py
@@ -0,0 +1,190 @@
+from amaranth.build import *
+
+
+__all__ = [
+ "SPIFlashResources", "SDCardResources",
+ "SRAMResource", "SDRAMResource", "NORFlashResources",
+ "DDR3Resource",
+]
+
+
+def SPIFlashResources(*args, cs_n, clk, copi, cipo, wp_n=None, hold_n=None,
+ conn=None, attrs=None):
+ resources = []
+
+ io_all = []
+ if attrs is not None:
+ io_all.append(attrs)
+ io_all.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn)))
+ io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
+
+ io_1x = list(io_all)
+ io_1x.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
+ io_1x.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
+ if wp_n is not None and hold_n is not None:
+ io_1x.append(Subsignal("wp", PinsN(wp_n, dir="o", conn=conn, assert_width=1)))
+ io_1x.append(Subsignal("hold", PinsN(hold_n, dir="o", conn=conn, assert_width=1)))
+ resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
+ name_suffix="1x"))
+
+ io_2x = list(io_all)
+ io_2x.append(Subsignal("dq", Pins(" ".join([copi, cipo]), dir="io", conn=conn,
+ assert_width=2)))
+ resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
+ name_suffix="2x"))
+
+ if wp_n is not None and hold_n is not None:
+ io_4x = list(io_all)
+ io_4x.append(Subsignal("dq", Pins(" ".join([copi, cipo, wp_n, hold_n]), dir="io", conn=conn,
+ assert_width=4)))
+ resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
+ name_suffix="4x"))
+
+ return resources
+
+
+def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=None, wp_n=None,
+ conn=None, attrs=None):
+ resources = []
+
+ io_common = []
+ if attrs is not None:
+ io_common.append(attrs)
+ if cd is not None:
+ io_common.append(Subsignal("cd", Pins(cd, dir="i", conn=conn, assert_width=1)))
+ if wp_n is not None:
+ io_common.append(Subsignal("wp", PinsN(wp_n, dir="i", conn=conn, assert_width=1)))
+
+ io_native = list(io_common)
+ io_native.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
+ io_native.append(Subsignal("cmd", Pins(cmd, dir="o", conn=conn, assert_width=1)))
+
+ io_1bit = list(io_native)
+ io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", conn=conn, assert_width=1)))
+ if dat3 is not None:
+ # DAT3 has a pullup and works as electronic card detect
+ io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", conn=conn, assert_width=1)))
+ resources.append(Resource.family(*args, default_name="sd_card", ios=io_1bit,
+ name_suffix="1bit"))
+
+ if dat1 is not None and dat2 is not None and dat3 is not None:
+ io_4bit = list(io_native)
+ io_4bit.append(Subsignal("dat", Pins(" ".join((dat0, dat1, dat2, dat3)), dir="io",
+ conn=conn, assert_width=4)))
+ resources.append(Resource.family(*args, default_name="sd_card", ios=io_4bit,
+ name_suffix="4bit"))
+
+ if dat3 is not None:
+ io_spi = list(io_common)
+ # DAT3/CS# has a pullup and doubles as electronic card detect
+ io_spi.append(Subsignal("cs", PinsN(dat3, dir="io", conn=conn, assert_width=1)))
+ io_spi.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
+ io_spi.append(Subsignal("copi", Pins(cmd, dir="o", conn=conn, assert_width=1)))
+ io_spi.append(Subsignal("cipo", Pins(dat0, dir="i", conn=conn, assert_width=1)))
+ resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi,
+ name_suffix="spi"))
+
+ return resources
+
+
+def SRAMResource(*args, cs_n, oe_n=None, we_n, a, d, dm_n=None,
+ conn=None, attrs=None):
+ io = []
+ io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+ if oe_n is not None:
+ # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
+ io.append(Subsignal("oe", PinsN(oe_n, dir="o", conn=conn, assert_width=1)))
+ io.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
+ io.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
+ io.append(Subsignal("d", Pins(d, dir="io", conn=conn)))
+ if dm_n is not None:
+ io.append(Subsignal("dm", PinsN(dm_n, dir="o", conn=conn))) # dm="LB# UB#"
+ if attrs is not None:
+ io.append(attrs)
+ return Resource.family(*args, default_name="sram", ios=io)
+
+
+def SDRAMResource(*args, clk, cke=None, cs_n=None, we_n, ras_n, cas_n, ba, a, dq, dqm=None,
+ conn=None, attrs=None):
+ io = []
+ io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
+ if cke is not None:
+ io.append(Subsignal("clk_en", Pins(cke, dir="o", conn=conn, assert_width=1)))
+ if cs_n is not None:
+ io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+ io.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
+ io.append(Subsignal("ras", PinsN(ras_n, dir="o", conn=conn, assert_width=1)))
+ io.append(Subsignal("cas", PinsN(cas_n, dir="o", conn=conn, assert_width=1)))
+ io.append(Subsignal("ba", Pins(ba, dir="o", conn=conn)))
+ io.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
+ io.append(Subsignal("dq", Pins(dq, dir="io", conn=conn)))
+ if dqm is not None:
+ io.append(Subsignal("dqm", Pins(dqm, dir="o", conn=conn))) # dqm="LDQM# UDQM#"
+ if attrs is not None:
+ io.append(attrs)
+ return Resource.family(*args, default_name="sdram", ios=io)
+
+
+def NORFlashResources(*args, rst=None, byte_n=None, cs_n, oe_n, we_n, wp_n, by, a, dq,
+ conn=None, attrs=None):
+ resources = []
+
+ io_common = []
+ if rst is not None:
+ io_common.append(Subsignal("rst", Pins(rst, dir="o", conn=conn, assert_width=1)))
+ io_common.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+ io_common.append(Subsignal("oe", PinsN(oe_n, dir="o", conn=conn, assert_width=1)))
+ io_common.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
+ io_common.append(Subsignal("wp", PinsN(wp_n, dir="o", conn=conn, assert_width=1)))
+ io_common.append(Subsignal("rdy", Pins(by, dir="i", conn=conn, assert_width=1)))
+
+ if byte_n is None:
+ io_8bit = list(io_common)
+ io_8bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
+ io_8bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=8)))
+ resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
+ name_suffix="8bit"))
+ else:
+ *dq_0_14, dq15_am1 = dq.split()
+
+ # If present in a requested resource, this pin needs to be strapped correctly.
+ io_common.append(Subsignal("byte", PinsN(byte_n, dir="o", conn=conn, assert_width=1)))
+
+ io_8bit = list(io_common)
+ io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o", conn=conn)))
+ io_8bit.append(Subsignal("dq", Pins(" ".join(dq_0_14[:8]), dir="io", conn=conn,
+ assert_width=8)))
+ resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
+ name_suffix="8bit"))
+
+ io_16bit = list(io_common)
+ io_16bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
+ io_16bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=16)))
+ resources.append(Resource.family(*args, default_name="nor_flash", ios=io_16bit,
+ name_suffix="16bit"))
+
+ return resources
+
+
+def DDR3Resource(*args, rst_n=None, clk_p, clk_n, clk_en, cs_n, we_n, ras_n, cas_n, a, ba, dqs_p, dqs_n, dq, dm, odt,
+ conn=None, diff_attrs=None, attrs=None):
+ ios = []
+
+ ios.append(Subsignal("rst", PinsN(rst_n, dir="o", conn=conn, assert_width=1)))
+ ios.append(Subsignal("clk", DiffPairs(clk_p, clk_n, dir="o", conn=conn, assert_width=1), diff_attrs))
+ ios.append(Subsignal("clk_en", Pins(clk_en, dir="o", conn=conn, assert_width=1)))
+ ios.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+ ios.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
+ ios.append(Subsignal("ras", PinsN(ras_n, dir="o", conn=conn, assert_width=1)))
+ ios.append(Subsignal("cas", PinsN(cas_n, dir="o", conn=conn, assert_width=1)))
+ ios.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
+ ios.append(Subsignal("ba", Pins(ba, dir="o", conn=conn)))
+ ios.append(Subsignal("dqs", DiffPairs(dqs_p, dqs_n, dir="io", conn=conn), diff_attrs))
+ ios.append(Subsignal("dq", Pins(dq, dir="io", conn=conn)))
+ ios.append(Subsignal("dm", Pins(dm, dir="o", conn=conn)))
+ ios.append(Subsignal("odt", Pins(odt, dir="o", conn=conn, assert_width=1)))
+
+ if attrs is not None:
+ ios.append(attrs)
+
+ return Resource.family(*args, default_name="ddr3", ios=ios)
diff --git a/amaranth_boards/resources/user.py b/amaranth_boards/resources/user.py
new file mode 100644
index 0000000..046f122
--- /dev/null
+++ b/amaranth_boards/resources/user.py
@@ -0,0 +1,43 @@
+from amaranth.build import *
+
+
+__all__ = ["LEDResources", "RGBLEDResource", "ButtonResources", "SwitchResources"]
+
+
+def _SplitResources(*args, pins, invert=False, conn=None, attrs=None, default_name, dir):
+ assert isinstance(pins, (str, list, dict))
+
+ if isinstance(pins, str):
+ pins = pins.split()
+ if isinstance(pins, list):
+ pins = dict(enumerate(pins))
+
+ resources = []
+ for number, pin in pins.items():
+ ios = [Pins(pin, dir=dir, invert=invert, conn=conn)]
+ if attrs is not None:
+ ios.append(attrs)
+ resources.append(Resource.family(*args, number, default_name=default_name, ios=ios))
+ return resources
+
+
+def LEDResources(*args, **kwargs):
+ return _SplitResources(*args, **kwargs, default_name="led", dir="o")
+
+
+def RGBLEDResource(*args, r, g, b, invert=False, conn=None, attrs=None):
+ ios = []
+ ios.append(Subsignal("r", Pins(r, dir="o", invert=invert, conn=conn, assert_width=1)))
+ ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, conn=conn, assert_width=1)))
+ ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, conn=conn, assert_width=1)))
+ if attrs is not None:
+ ios.append(attrs)
+ return Resource.family(*args, default_name="rgb_led", ios=ios)
+
+
+def ButtonResources(*args, **kwargs):
+ return _SplitResources(*args, **kwargs, default_name="button", dir="i")
+
+
+def SwitchResources(*args, **kwargs):
+ return _SplitResources(*args, **kwargs, default_name="switch", dir="i")
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-26 23:27:20 +0000