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-rw-r--r--nmigen_boards/dev/sram.py6
1 files changed, 4 insertions, 2 deletions
diff --git a/nmigen_boards/dev/sram.py b/nmigen_boards/dev/sram.py
index 4eb4eca..14e31ce 100644
--- a/nmigen_boards/dev/sram.py
+++ b/nmigen_boards/dev/sram.py
@@ -4,10 +4,12 @@ from nmigen.build import *
__all__ = ["SRAMResource"]
-def SRAMResource(*args, cs, oe, we, a, d, dm=None, attrs=None):
+def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
io = []
io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
- io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
+ if oe is not None:
+ # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
+ io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
io.append(Subsignal("a", Pins(a, dir="o")))
io.append(Subsignal("d", Pins(d, dir="io")))