1 files changed, 10 insertions, 6 deletions
diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py
index 9710ffb..8d5bd7e 100644
--- a/nmigen_boards/resources/interface.py
+++ b/nmigen_boards/resources/interface.py
@@ -59,18 +59,23 @@ def IrDAResource(number, *, rx, tx, en=None, sd=None,
 def SPIResource(*args, cs, clk, copi, cipo, int=None, reset=None,
                 conn=None, attrs=None, role="controller"):
     assert role in ("controller", "peripheral")
+    assert copi is not None or cipo is not None # support unidirectional SPI
 
     io = []
     if role == "controller":
         io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn)))
         io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
-        io.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
-        io.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
+        if copi is not None:
+            io.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
+        if cipo is not None:
+            io.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
     else:  # peripheral
         io.append(Subsignal("cs", PinsN(cs, dir="i", conn=conn, assert_width=1)))
         io.append(Subsignal("clk", Pins(clk, dir="i", conn=conn, assert_width=1)))
-        io.append(Subsignal("copi", Pins(copi, dir="i", conn=conn, assert_width=1)))
-        io.append(Subsignal("cipo", Pins(cipo, dir="oe", conn=conn, assert_width=1)))
+        if copi is not None:
+            io.append(Subsignal("copi", Pins(copi, dir="i", conn=conn, assert_width=1)))
+        if cipo is not None:
+            io.append(Subsignal("cipo", Pins(cipo, dir="oe", conn=conn, assert_width=1)))
     if int is not None:
         if role == "controller":
             io.append(Subsignal("int", Pins(int, dir="i", conn=conn)))
@@ -95,8 +100,7 @@ def I2CResource(*args, scl, sda, conn=None, attrs=None):
     return Resource.family(*args, default_name="i2c", ios=io)
 
 
-def DirectUSBResource(*args, d_p, d_n, pullup=None, vbus_valid=None,
-    conn=None, attrs=None):
+def DirectUSBResource(*args, d_p, d_n, pullup=None, vbus_valid=None, conn=None, attrs=None):
 
     io = []
     io.append(Subsignal("d_p", Pins(d_p, dir="io", conn=conn, assert_width=1)))