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authormyrtle <gatecat@ds0.me>2023-12-12 13:01:19 +0100
committerGitHub <noreply@github.com>2023-12-12 13:01:19 +0100
commit1a40ae75d4eebee9cce73a2c4d634fd42ed0110f (patch)
tree689bb2e89ba34966438d47acfdfc56b0f50acc6d
parentd20a5e9001f46262bf0cef220f1a6943946e421d (diff)
parentcfc6e9fdf70e0c788ad12b7f58237b02deb9d1e1 (diff)
Merge pull request #313 from YosysHQ/gatecat/bram-doc-update
Update BRAM NegClk info based on latest testing
-rw-r--r--docs/ram_tile.html4
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/ram_tile.html b/docs/ram_tile.html
index 73bda8d..2264966 100644
--- a/docs/ram_tile.html
+++ b/docs/ram_tile.html
@@ -91,8 +91,8 @@ The read/write mode selects the width of the read/write port:
</table>
<p>
-The <span style="font-family:monospace">NegClk</span> bit in the RAMB tile negates the polarity of the <span style="font-family:monospace">WCLK</span> port,
-and the <span style="font-family:monospace">NegClk</span> bit in the RAMT tile negates the polarity of the <span style="font-family:monospace">RCLK</span> port.
+The <span style="font-family:monospace">NegClk</span> bit in the RAMB tile (1k die) or RAMT tile (other devices) negates the polarity of the <span style="font-family:monospace">WCLK</span> port,
+and the <span style="font-family:monospace">NegClk</span> bit in the RAMT (1k die) or RAMB tile (other devices) tile negates the polarity of the <span style="font-family:monospace">RCLK</span> port.
</p>
<p>