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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-06 14:57:28 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-06 15:02:16 +0100 |
| commit | d3a753f7d747b007f464a831d6b2b21e87991e46 (patch) | |
| tree | 3f20fd5c95294e4dd76ed628e602e5ba0316fbdf /examples/icebreaker/Makefile | |
| parent | 722790ad3cdb497e1b13cd1b4368d8380371eb37 (diff) | |
Add icebreaker example project
Diffstat (limited to 'examples/icebreaker/Makefile')
| -rw-r--r-- | examples/icebreaker/Makefile | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/examples/icebreaker/Makefile b/examples/icebreaker/Makefile new file mode 100644 index 0000000..e91de63 --- /dev/null +++ b/examples/icebreaker/Makefile @@ -0,0 +1,46 @@ +PROJ = example + +PIN_DEF = icebreaker.pcf +DEVICE = up5k + +all: $(PROJ).rpt $(PROJ).bin + +%.blif: %.v + yosys -p 'synth_ice40 -top top -blif $@' $< + +%.asc: $(PIN_DEF) %.blif + arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^ + +%.bin: %.asc + icepack $< $@ + +%.rpt: %.asc + icetime -d $(DEVICE) -mtr $@ $< + +%_tb: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb + vvp -N $< +vcd=$@ + +%_syn.v: %.blif + yosys -p 'read_blif -wideports $^; write_verilog $@' + +%_syntb: %_tb.v %_syn.v + iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + +%_syntb.vcd: %_syntb + vvp -N $< +vcd=$@ + +prog: $(PROJ).bin + iceprog $< + +sudo-prog: $(PROJ).bin + @echo 'Executing prog as root!!!' + sudo iceprog $< + +clean: + rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin + +.SECONDARY: +.PHONY: all prog clean |