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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-31 14:57:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-31 14:57:24 +0200 |
| commit | 872e333cf75c6fc1bdf985f09565c70d16567434 (patch) | |
| tree | 11a7b2336faaf12e84d8890c1674c04b0c8093a6 /examples/icestick/Makefile | |
| parent | f704149b7298c7c6b56520d104dc4b20abf455b2 (diff) | |
| parent | 81e943e050dad652da795d21375bb700064116f4 (diff) | |
Merge branch 'master' into ice5k
Diffstat (limited to 'examples/icestick/Makefile')
| -rw-r--r-- | examples/icestick/Makefile | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile index 9294608..8b8e741 100644 --- a/examples/icestick/Makefile +++ b/examples/icestick/Makefile @@ -1,5 +1,6 @@ PROJ = example # PROJ = rs232demo +# PROJ = checker PIN_DEF = icestick.pcf DEVICE = hx1k @@ -18,6 +19,21 @@ all: $(PROJ).rpt $(PROJ).bin %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< +%_tb: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb + vvp -N $< +vcd=$@ + +%_syn.v: %.blif + yosys -p 'read_blif -wideports $^; write_verilog $@' + +%_syntb: %_tb.v %_syn.v + iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + +%_syntb.vcd: %_syntb + vvp -N $< +vcd=$@ + prog: $(PROJ).bin iceprog $< |