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| author | Clifford Wolf <clifford@clifford.at> | 2017-03-08 13:31:32 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-03-08 13:31:32 +0100 |
| commit | a2e8c06d688150c319d87e07e103a3178a96690a (patch) | |
| tree | f48f99ed6412fd3dcc4526345ebb2f75e2541060 /icefuzz/make_fflogic.py | |
| parent | cdaab84e638cd5ea6a07860465198e19003127a6 (diff) | |
Remove some trailing whitespaces
Diffstat (limited to 'icefuzz/make_fflogic.py')
| -rw-r--r-- | icefuzz/make_fflogic.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/icefuzz/make_fflogic.py b/icefuzz/make_fflogic.py index 5eae704..ecca7ca 100644 --- a/icefuzz/make_fflogic.py +++ b/icefuzz/make_fflogic.py @@ -37,7 +37,7 @@ def print_seq_op(dst, src1, src2, op, f): for idx in range(num): with open("work_fflogic/fflogic_%02d.v" % idx, "w") as f: - if os.getenv('ICE384PINS'): + if os.getenv('ICE384PINS'): print("module top(input clk, rst, en, input [1:0] a, b, c, d, output [1:0] y, output z);", file=f) print(" reg [1:0] p, q;", file=f) else: |