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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-18 13:10:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-18 13:10:40 +0200 |
| commit | 48154cb6f452d3bdb4da36cc267b4b6c45588dc9 (patch) | |
| tree | 3ec3be9ef7e8db1fb7c764ed8202e0215a8eb7c7 /icefuzz/tests/colbuf_ram_8k.sh | |
| parent | 13e63e6b65e044e348356731b55610d02cb308b9 (diff) | |
Imported full dev sources
Diffstat (limited to 'icefuzz/tests/colbuf_ram_8k.sh')
| -rw-r--r-- | icefuzz/tests/colbuf_ram_8k.sh | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/icefuzz/tests/colbuf_ram_8k.sh b/icefuzz/tests/colbuf_ram_8k.sh new file mode 100644 index 0000000..56c5825 --- /dev/null +++ b/icefuzz/tests/colbuf_ram_8k.sh @@ -0,0 +1,57 @@ +#!/bin/bash + +set -ex + +mkdir -p colbuf_ram_8k.work +cd colbuf_ram_8k.work + +glb_pins="C8 F7 G1 H11 H16 J3 K9 R9" + +for x in 8 25; do +for y in {1..32}; do + pf="colbuf_ram_8k_${x}_${y}" + gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; ) + if [ $((y % 2)) == 1 ]; then + clkport="WCLK" + other_clkport="RCLK" + else + clkport="RCLK" + other_clkport="WCLK" + fi + cat > ${pf}.v <<- EOT + module top (input c, oc, input [1:0] d, output [1:0] q); + wire gc; + SB_GB_IO #( + .PIN_TYPE(6'b 0000_00), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0), + .IO_STANDARD("SB_LVCMOS") + ) gbuf ( + .PACKAGE_PIN(c), + .GLOBAL_BUFFER_OUTPUT(gc) + ); + SB_RAM40_4K #( + .READ_MODE(3), + .WRITE_MODE(3) + ) ram40 ( + .WADDR(11'b0), + .RADDR(11'b0), + .$clkport(gc), + .$other_clkport(oc), + .RDATA(q), + .WDATA(d), + .WE(1'b1), + .WCLKE(1'b1), + .RE(1'b1), + .RCLKE(1'b1) + ); + endmodule + EOT + echo "set_location ram40 $x $((y - (1 - y%2))) 0" > ${pf}.pcf + echo "set_io oc 1" >> ${pf}.pcf + echo "set_io c $gpin" >> ${pf}.pcf + ICEDEV=hx8k-ct256 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 + ../../../icebox/icebox_explain.py ${pf}.txt > ${pf}.exp + rm -rf ${pf}.tmp +done; done + |