Add some verilog tests for analysing up5k features

1 files changed, 25 insertions, 0 deletions

diff --git a/icefuzz/tests/sb_spram256ka.v b/icefuzz/tests/sb_spram256ka.v
new file mode 100644
index 0000000..e1e1403
--- /dev/null
+++ b/icefuzz/tests/sb_spram256ka.v
@@ -0,0 +1,25 @@
+module top(
+  input clk,
+  input [13:0] addr,
+  input [7:0] din,
+  input wren,
+  input cs,
+  output [7:0] dout
+);
+
+SB_SPRAM256KA spram_i
+  (
+    .ADDRESS(addr),
+    .DATAIN(din),
+    .MASKWREN(4'b1111),
+    .WREN(wren),
+    .CHIPSELECT(cs),
+    .CLOCK(clk),
+    .STANDBY(1'b0),
+    .SLEEP(1'b0),
+    .POWEROFF(1'b0),
+    .DATAOUT(dout)
+  );
+  
+
+endmodule
\ No newline at end of file