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-rw-r--r--examples/icestick/Makefile7
1 files changed, 4 insertions, 3 deletions
diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile
index d687d14..8b8e741 100644
--- a/examples/icestick/Makefile
+++ b/examples/icestick/Makefile
@@ -1,5 +1,6 @@
PROJ = example
# PROJ = rs232demo
+# PROJ = checker
PIN_DEF = icestick.pcf
DEVICE = hx1k
@@ -22,16 +23,16 @@ all: $(PROJ).rpt $(PROJ).bin
iverilog -o $@ $^
%_tb.vcd: %_tb
- ./$< +vcd=$@
+ vvp -N $< +vcd=$@
%_syn.v: %.blif
- yosys -o $@ $^
+ yosys -p 'read_blif -wideports $^; write_verilog $@'
%_syntb: %_tb.v %_syn.v
iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
%_syntb.vcd: %_syntb
- ./$< +vcd=$@
+ vvp -N $< +vcd=$@
prog: $(PROJ).bin
iceprog $<