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path: root/icebox/icebox.py
AgeCommit message (Collapse)Author
2025-06-03Update Claire's name and fix the reference image in the iceprog helpMatt Venn
2024-12-11Resolve warning with python 3.12Miodrag Milanovic
2023-02-01icebox: Add PLL ICEGATE functionSylvain Munaut
Only tested on UP5k. For others, it was just deduced. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-25icebox: cb121 does have a PLLgatecat
Signed-off-by: gatecat <gatecat@ds0.me>
2020-12-04added I2C and SPI for u4k to databaseNils Albartus
2020-06-03icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5kSylvain Munaut
This allows selection of the div-by-5 mode of the PLL. This bit can't be fuzzed because it's not supported by the lattice tools at all ... This only works for sure on the UP5k. I tested HX8k and it didn't support it, so I'm only adding this on the known working FPGA. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-07-03up5k: Fix TOPADDSUB_CARRYSELECT_0 override where it swaps with osc trimmingDavid Shah
Signed-off-by: David Shah <dave@ds0.me>
2019-06-10add RGB_DRV/LED_DRV_CUR for u4kSimon Schubert
2019-06-08icebox: Use cached re functionsMichael Buesch
2019-06-08icebox: Add helper functions to LRU cache regular expression resultsMichael Buesch
2019-06-08icebox: Use LRU cache for often called function tile_has_net()Michael Buesch
2019-02-22u4k: add SMCCLK cell locationSimon Schubert
icecube uses SMCCLK.CLK to "legalize" output cells. Unclear what this is for, but it appears in almost all outputs.
2019-02-22iCE40 Ultra = iCE5LP = u4k portSimon Schubert
2018-10-10Merge pull request #178 from elmsfu/hlc/add_symbols_supportClifford Wolf
hlc: parse '.sym>' to track signal names from HLC to ASC
2018-08-28Add support for cm36 and swg25tr lm4k packages.Andrew Wygle
2018-07-26icebox: parse '.sym>' HLC to track signal namesElms
2018-05-30icebox: Allow selecting package in icebox_vlogDavid Shah
Signed-off-by: David Shah <davey1576@gmail.com>
2018-05-13Correct internal global buffers for lm4kAndrew Wygle
2018-05-13Added missing ieren entries for lm4k.Andrew Wygle
Config SPI pins weren't present in ioctrl_lm4k.sh
2018-05-13Support lm4k in icebox_chipdb.py.Andrew Wygle
2018-05-12Completed first pass at icebox support for lm4k.Andrew Wygle
Needs testing.
2018-05-12[WIP] Added colbuf and gbufin data for LM seriesAndrew Wygle
2018-05-12[WIP] Add partial icebox support for lm4k.Andrew Wygle
2018-04-02Add BG121 package variant and update docsDavid Shah
2018-02-09Add UltraPlus I³C IO to chipdbDavid Shah
2018-02-09Add RGB driver outputs to chipdbDavid Shah
2018-01-16Add 5k UWG30 ieren data to dbDavid Shah
2018-01-16Remove seperate 5k RAM DB and share with 8k insteadDavid Shah
This should ensure that the 5k RAM routing entries are now complete, fixing #115
2018-01-16Add pinout for 5k UWG30 packageDavid Shah
2018-01-16HFOSC trimming infoDavid Shah
2018-01-16New UltraPlus corner tracing algorithmDavid Shah
2018-01-16Misc routing tweaksDavid Shah
2018-01-16Figure out missing SPI config bits, and add to chipdbDavid Shah
2017-11-26Chipdb fix for hard IPDavid Shah
2017-11-24Add UltraPlus IP to chipdbDavid Shah
2017-11-23Begin I2C/SPI IP reverse engineeringDavid Shah
2017-11-20Fix whitespace and a couple of typosDavid Shah
2017-11-18Add all cf_bits and pullup strength notesDavid Shah
2017-11-17Remove non-existing routing resources (5k)David Shah
2017-11-17Add support for UltraPlus SPRAMDavid Shah
2017-11-17Add UltraPlus LED driver support and demoDavid Shah
2017-11-17UltraPlus Internal Oscillator supportDavid Shah
2017-11-17UltraPlus DSPs workingDavid Shah
2017-11-17Add new tile types and MAC16s to chipdbDavid Shah
2017-11-17Tidy up some of the icebox changesDavid Shah
2017-11-17Fix 5k corner routing, and reverse engineer SPRAMDavid Shah
2017-11-17Start UltraPlus DSP documentationDavid Shah
2017-11-17Trace DSP routingDavid Shah
2017-11-06Fix 5k gbin configurationDavid Shah
2017-11-05Fix 5k padin_glb_netwk bitsDavid Shah
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