icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Age	Commit message (Expand)	Author
2018-01-16	Remove seperate 5k RAM DB and share with 8k instead	David Shah
2017-11-17	Add missing 5k BRAM bits	David Shah
2017-11-17	Trace DSP routing	David Shah
2017-11-05	Add more 5k RAM bits to db	David Shah
2017-10-29	Share glb_netwk data between 5k and 8k parts	David Shah
2017-10-25	Add ColBufCtrl bits to database for 5k parts	David Shah
2017-10-21	Swap IEREN for pin 26 to get example working, other inputs still need fixing	David Shah
2017-10-20	Modify icebox.py so it generates a 5k chipdb	David Shah
2017-07-31	Remove extra IoCtrl cf_bit_ and extra_padeb_test_ lines from database	Clifford Wolf
2017-07-07	Work in progress DB. Having trouble getting group_segments to work without er...	Scott Shawcroft
2016-01-16	icefuzz improvements, refuzz timings	Clifford Wolf
2016-01-09	Fuzzed RamCascade bits	Clifford Wolf
2015-12-04	Added lutff_i/lout net to model	Clifford Wolf
2015-10-06	Added 8k timing data	Clifford Wolf
2015-10-02	more database updates	Clifford Wolf
2015-09-27	database updates	Clifford Wolf
2015-07-18	Imported full dev sources	Clifford Wolf
2015-07-18	Import of icestorm-snapshot-150526.zip	Clifford Wolf
2015-07-18	Import of icestorm-snapshot-150413.zip	Clifford Wolf
2015-07-18	Import of icestorm-snapshot-150322.zip	Clifford Wolf