| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-01-16 | Remove seperate 5k RAM DB and share with 8k instead | David Shah | |
| This should ensure that the 5k RAM routing entries are now complete, fixing #115 | |||
| 2017-11-17 | Add missing 5k BRAM bits | David Shah | |
| 2017-11-17 | Create icefuzz scripts for DSP and 5k | David Shah | |
| 2017-11-05 | Add more 5k RAM bits to db | David Shah | |
| 2017-07-02 | Introduce device class into fuxx workign directories and have glbcheck ↵ | Scott Shawcroft | |
| handle unsupported 5k tiles ok. | |||
| 2017-06-22 | Add icefuzz support for the UP5K and rework underlying device specification ↵ | Scott Shawcroft | |
| for more flexibility. | |||
 |
index : icestorm | |
| Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered) |
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