First commit

2 files changed, 732 insertions, 0 deletions

diff --git a/drivers/enet/Cargo.toml b/drivers/enet/Cargo.toml
new file mode 100644
index 0000000..3c7d630
--- /dev/null
+++ b/drivers/enet/Cargo.toml
@@ -0,0 +1,7 @@
+[package]
+name = "imxrt-drivers-enet"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+ral-registers = { workspace = true }
diff --git a/drivers/enet/src/lib.rs b/drivers/enet/src/lib.rs
new file mode 100644
index 0000000..409d252
--- /dev/null
+++ b/drivers/enet/src/lib.rs
@@ -0,0 +1,725 @@
+#![no_std]
+
+#[repr(C)]
+#[allow(non_snake_case)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x04],
+    #[doc = "Interrupt Event Register"]
+    pub EIR: u32,
+    #[doc = "Interrupt Mask Register"]
+    pub EIMR: u32,
+    _reserved1: [u8; 0x04],
+    #[doc = "Receive Descriptor Active Register - Ring 0"]
+    pub RDAR: u32,
+    #[doc = "Transmit Descriptor Active Register - Ring 0"]
+    pub TDAR: u32,
+    _reserved2: [u8; 0x0c],
+    #[doc = "Ethernet Control Register"]
+    pub ECR: u32,
+    _reserved3: [u8; 0x18],
+    #[doc = "MII Management Frame Register"]
+    pub MMFR: u32,
+    #[doc = "MII Speed Control Register"]
+    pub MSCR: u32,
+    _reserved4: [u8; 0x1c],
+    #[doc = "MIB Control Register"]
+    pub MIBC: u32,
+    _reserved5: [u8; 0x1c],
+    #[doc = "Receive Control Register"]
+    pub RCR: u32,
+    _reserved6: [u8; 0x3c],
+    #[doc = "Transmit Control Register"]
+    pub TCR: u32,
+    _reserved7: [u8; 0x1c],
+    #[doc = "Physical Address Lower Register"]
+    pub PALR: u32,
+    #[doc = "Physical Address Upper Register"]
+    pub PAUR: u32,
+    #[doc = "Opcode/Pause Duration Register"]
+    pub OPD: u32,
+    #[doc = "Transmit Interrupt Coalescing Register"]
+    pub TXIC: [u32; 3usize],
+    _reserved8: [u8; 0x04],
+    #[doc = "Receive Interrupt Coalescing Register"]
+    pub RXIC: [u32; 3usize],
+    _reserved9: [u8; 0x0c],
+    #[doc = "Descriptor Individual Upper Address Register"]
+    pub IAUR: u32,
+    #[doc = "Descriptor Individual Lower Address Register"]
+    pub IALR: u32,
+    #[doc = "Descriptor Group Upper Address Register"]
+    pub GAUR: u32,
+    #[doc = "Descriptor Group Lower Address Register"]
+    pub GALR: u32,
+    _reserved10: [u8; 0x1c],
+    #[doc = "Transmit FIFO Watermark Register"]
+    pub TFWR: u32,
+    _reserved11: [u8; 0x18],
+    #[doc = "Receive Descriptor Ring 1 Start Register"]
+    pub RDSR1: u32,
+    #[doc = "Transmit Buffer Descriptor Ring 1 Start Register"]
+    pub TDSR1: u32,
+    #[doc = "Maximum Receive Buffer Size Register - Ring 1"]
+    pub MRBR1: u32,
+    #[doc = "Receive Descriptor Ring 2 Start Register"]
+    pub RDSR2: u32,
+    #[doc = "Transmit Buffer Descriptor Ring 2 Start Register"]
+    pub TDSR2: u32,
+    #[doc = "Maximum Receive Buffer Size Register - Ring 2"]
+    pub MRBR2: u32,
+    _reserved12: [u8; 0x08],
+    #[doc = "Receive Descriptor Ring 0 Start Register"]
+    pub RDSR: u32,
+    #[doc = "Transmit Buffer Descriptor Ring 0 Start Register"]
+    pub TDSR: u32,
+    #[doc = "Maximum Receive Buffer Size Register - Ring 0"]
+    pub MRBR: u32,
+    _reserved13: [u8; 0x04],
+    #[doc = "Receive FIFO Section Full Threshold"]
+    pub RSFL: u32,
+    #[doc = "Receive FIFO Section Empty Threshold"]
+    pub RSEM: u32,
+    #[doc = "Receive FIFO Almost Empty Threshold"]
+    pub RAEM: u32,
+    #[doc = "Receive FIFO Almost Full Threshold"]
+    pub RAFL: u32,
+    #[doc = "Transmit FIFO Section Empty Threshold"]
+    pub TSEM: u32,
+    #[doc = "Transmit FIFO Almost Empty Threshold"]
+    pub TAEM: u32,
+    #[doc = "Transmit FIFO Almost Full Threshold"]
+    pub TAFL: u32,
+    #[doc = "Transmit Inter-Packet Gap"]
+    pub TIPG: u32,
+    #[doc = "Frame Truncation Length"]
+    pub FTRL: u32,
+    _reserved14: [u8; 0x0c],
+    #[doc = "Transmit Accelerator Function Configuration"]
+    pub TACC: u32,
+    #[doc = "Receive Accelerator Function Configuration"]
+    pub RACC: u32,
+    #[doc = "Receive Classification Match Register for Class n"]
+    pub RCMR: [u32; 2usize],
+    _reserved15: [u8; 0x08],
+    #[doc = "DMA Class Based Configuration"]
+    pub DMACFG: [u32; 2usize],
+    #[doc = "Receive Descriptor Active Register - Ring 1"]
+    pub RDAR1: u32,
+    #[doc = "Transmit Descriptor Active Register - Ring 1"]
+    pub TDAR1: u32,
+    #[doc = "Receive Descriptor Active Register - Ring 2"]
+    pub RDAR2: u32,
+    #[doc = "Transmit Descriptor Active Register - Ring 2"]
+    pub TDAR2: u32,
+    #[doc = "QOS Scheme"]
+    pub QOS: u32,
+    _reserved16: [u8; 0x10],
+    #[doc = "Tx Packet Count Statistic Register"]
+    pub RMON_T_PACKETS: u32,
+    #[doc = "Tx Broadcast Packets Statistic Register"]
+    pub RMON_T_BC_PKT: u32,
+    #[doc = "Tx Multicast Packets Statistic Register"]
+    pub RMON_T_MC_PKT: u32,
+    #[doc = "Tx Packets with CRC/Align Error Statistic Register"]
+    pub RMON_T_CRC_ALIGN: u32,
+    #[doc = "Tx Packets Less Than Bytes and Good CRC Statistic Register"]
+    pub RMON_T_UNDERSIZE: u32,
+    #[doc = "Tx Packets GT MAX_FL bytes and Good CRC Statistic Register"]
+    pub RMON_T_OVERSIZE: u32,
+    #[doc = "Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register"]
+    pub RMON_T_FRAG: u32,
+    #[doc = "Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register"]
+    pub RMON_T_JAB: u32,
+    #[doc = "Tx Collision Count Statistic Register"]
+    pub RMON_T_COL: u32,
+    #[doc = "Tx 64-Byte Packets Statistic Register"]
+    pub RMON_T_P64: u32,
+    #[doc = "Tx 65- to 127-byte Packets Statistic Register"]
+    pub RMON_T_P65TO127: u32,
+    #[doc = "Tx 128- to 255-byte Packets Statistic Register"]
+    pub RMON_T_P128TO255: u32,
+    #[doc = "Tx 256- to 511-byte Packets Statistic Register"]
+    pub RMON_T_P256TO511: u32,
+    #[doc = "Tx 512- to 1023-byte Packets Statistic Register"]
+    pub RMON_T_P512TO1023: u32,
+    #[doc = "Tx 1024- to 2047-byte Packets Statistic Register"]
+    pub RMON_T_P1024TO2047: u32,
+    #[doc = "Tx Packets Greater Than 2048 Bytes Statistic Register"]
+    pub RMON_T_P_GTE2048: u32,
+    #[doc = "Tx Octets Statistic Register"]
+    pub RMON_T_OCTETS: u32,
+    #[doc = "Reserved Statistic Register"]
+    pub IEEE_T_DROP: u32,
+    #[doc = "Frames Transmitted OK Statistic Register"]
+    pub IEEE_T_FRAME_OK: u32,
+    #[doc = "Frames Transmitted with Single Collision Statistic Register"]
+    pub IEEE_T_1COL: u32,
+    #[doc = "Frames Transmitted with Multiple Collisions Statistic Register"]
+    pub IEEE_T_MCOL: u32,
+    #[doc = "Frames Transmitted after Deferral Delay Statistic Register"]
+    pub IEEE_T_DEF: u32,
+    #[doc = "Frames Transmitted with Late Collision Statistic Register"]
+    pub IEEE_T_LCOL: u32,
+    #[doc = "Frames Transmitted with Excessive Collisions Statistic Register"]
+    pub IEEE_T_EXCOL: u32,
+    #[doc = "Frames Transmitted with Tx FIFO Underrun Statistic Register"]
+    pub IEEE_T_MACERR: u32,
+    #[doc = "Frames Transmitted with Carrier Sense Error Statistic Register"]
+    pub IEEE_T_CSERR: u32,
+    #[doc = "Reserved Statistic Register"]
+    pub IEEE_T_SQE: u32,
+    #[doc = "Flow Control Pause Frames Transmitted Statistic Register"]
+    pub IEEE_T_FDXFC: u32,
+    #[doc = "Octet Count for Frames Transmitted w/o Error Statistic Register"]
+    pub IEEE_T_OCTETS_OK: u32,
+    _reserved17: [u8; 0x0c],
+    #[doc = "Rx Packet Count Statistic Register"]
+    pub RMON_R_PACKETS: u32,
+    #[doc = "Rx Broadcast Packets Statistic Register"]
+    pub RMON_R_BC_PKT: u32,
+    #[doc = "Rx Multicast Packets Statistic Register"]
+    pub RMON_R_MC_PKT: u32,
+    #[doc = "Rx Packets with CRC/Align Error Statistic Register"]
+    pub RMON_R_CRC_ALIGN: u32,
+    #[doc = "Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register"]
+    pub RMON_R_UNDERSIZE: u32,
+    #[doc = "Rx Packets Greater Than MAX_FL and Good CRC Statistic Register"]
+    pub RMON_R_OVERSIZE: u32,
+    #[doc = "Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register"]
+    pub RMON_R_FRAG: u32,
+    #[doc = "Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register"]
+    pub RMON_R_JAB: u32,
+    _reserved18: [u8; 0x04],
+    #[doc = "Rx 64-Byte Packets Statistic Register"]
+    pub RMON_R_P64: u32,
+    #[doc = "Rx 65- to 127-Byte Packets Statistic Register"]
+    pub RMON_R_P65TO127: u32,
+    #[doc = "Rx 128- to 255-Byte Packets Statistic Register"]
+    pub RMON_R_P128TO255: u32,
+    #[doc = "Rx 256- to 511-Byte Packets Statistic Register"]
+    pub RMON_R_P256TO511: u32,
+    #[doc = "Rx 512- to 1023-Byte Packets Statistic Register"]
+    pub RMON_R_P512TO1023: u32,
+    #[doc = "Rx 1024- to 2047-Byte Packets Statistic Register"]
+    pub RMON_R_P1024TO2047: u32,
+    #[doc = "Rx Packets Greater than 2048 Bytes Statistic Register"]
+    pub RMON_R_P_GTE2048: u32,
+    #[doc = "Rx Octets Statistic Register"]
+    pub RMON_R_OCTETS: u32,
+    #[doc = "Frames not Counted Correctly Statistic Register"]
+    pub IEEE_R_DROP: u32,
+    #[doc = "Frames Received OK Statistic Register"]
+    pub IEEE_R_FRAME_OK: u32,
+    #[doc = "Frames Received with CRC Error Statistic Register"]
+    pub IEEE_R_CRC: u32,
+    #[doc = "Frames Received with Alignment Error Statistic Register"]
+    pub IEEE_R_ALIGN: u32,
+    #[doc = "Receive FIFO Overflow Count Statistic Register"]
+    pub IEEE_R_MACERR: u32,
+    #[doc = "Flow Control Pause Frames Received Statistic Register"]
+    pub IEEE_R_FDXFC: u32,
+    #[doc = "Octet Count for Frames Received without Error Statistic Register"]
+    pub IEEE_R_OCTETS_OK: u32,
+    _reserved19: [u8; 0x011c],
+    #[doc = "Adjustable Timer Control Register"]
+    pub ATCR: u32,
+    #[doc = "Timer Value Register"]
+    pub ATVR: u32,
+    #[doc = "Timer Offset Register"]
+    pub ATOFF: u32,
+    #[doc = "Timer Period Register"]
+    pub ATPER: u32,
+    #[doc = "Timer Correction Register"]
+    pub ATCOR: u32,
+    #[doc = "Time-Stamping Clock Period Register"]
+    pub ATINC: u32,
+    #[doc = "Timestamp of Last Transmitted Frame"]
+    pub ATSTMP: u32,
+    _reserved20: [u8; 0x01e8],
+    #[doc = "Timer Global Status Register"]
+    pub TGSR: u32,
+    #[doc = "Timer Control Status Register"]
+    pub TCSR0: u32,
+    #[doc = "Timer Compare Capture Register"]
+    pub TCCR0: u32,
+    #[doc = "Timer Control Status Register"]
+    pub TCSR1: u32,
+    #[doc = "Timer Compare Capture Register"]
+    pub TCCR1: u32,
+    #[doc = "Timer Control Status Register"]
+    pub TCSR2: u32,
+    #[doc = "Timer Compare Capture Register"]
+    pub TCCR2: u32,
+    #[doc = "Timer Control Status Register"]
+    pub TCSR3: u32,
+    #[doc = "Timer Compare Capture Register"]
+    pub TCCR3: u32,
+}
+
+/// Transfer buffer descriptors.
+pub mod tx_bd {
+    use core::sync::atomic::{AtomicU16, AtomicU32};
+
+    /// Transfer descriptors.
+    #[repr(C)]
+    pub struct TxBD {
+        pub data_length: AtomicU16,
+        pub flags: AtomicU16,
+        pub data_buffer_pointer: AtomicU32,
+        pub errors: AtomicU16,
+        pub control: AtomicU16,
+        pub launch_time: AtomicU32,
+        _reserved0: [u8; 2],
+        pub last_bdu: AtomicU16,
+        pub timestamp_1588: AtomicU32,
+        _reserved1: [u8; 8],
+    }
+
+    pub const FLAGS_READY: u16 = 1 << 15;
+    pub const FLAGS_WRAP: u16 = 1 << 13;
+    pub const FLAGS_LAST_IN_FRAME: u16 = 1 << 11;
+    pub const FLAGS_TRANSMIT_CRC: u16 = 1 << 10;
+
+    pub const CONTROL_INT: u16 = 1 << 14;
+
+    pub const ZEROED: TxBD = TxBD {
+        data_length: AtomicU16::new(0),
+        flags: AtomicU16::new(0),
+        data_buffer_pointer: AtomicU32::new(0),
+        errors: AtomicU16::new(0),
+        control: AtomicU16::new(0),
+        launch_time: AtomicU32::new(0),
+        _reserved0: [0; 2],
+        last_bdu: AtomicU16::new(0),
+        timestamp_1588: AtomicU32::new(0),
+        _reserved1: [0; 8],
+    };
+}
+
+/// Receive buffer descriptors.
+pub mod rx_bd {
+    use core::sync::atomic::{AtomicU16, AtomicU32};
+
+    /// Receive descriptors.
+    #[repr(C)]
+    pub struct RxBD {
+        pub data_length: AtomicU16,
+        pub flags: AtomicU16,
+        pub data_buffer_pointer: AtomicU32,
+        pub status: AtomicU16,
+        pub control: AtomicU16,
+        pub checksum: AtomicU16,
+        pub header: AtomicU16,
+        _reserved0: [u8; 2],
+        pub last_bdu: AtomicU16,
+        pub timestamp_1588: AtomicU32,
+        _reserved1: [u8; 8],
+    }
+
+    pub const FLAGS_EMPTY: u16 = 1 << 15;
+    pub const FLAGS_RECEIVE_OWNERSHP_1: u16 = 1 << 14;
+    pub const FLAGS_WRAP: u16 = 1 << 13;
+    pub const FLAGS_RECEIVE_OWNERSHP_2: u16 = 1 << 12;
+    pub const FLAGS_LAST: u16 = 1 << 11;
+
+    pub const CONTROL_INT: u16 = 1 << 7;
+
+    pub const ZEROED: RxBD = RxBD {
+        data_length: AtomicU16::new(0),
+        flags: AtomicU16::new(0),
+        data_buffer_pointer: AtomicU32::new(0),
+        status: AtomicU16::new(0),
+        control: AtomicU16::new(0),
+        checksum: AtomicU16::new(0),
+        header: AtomicU16::new(0),
+        _reserved0: [0; 2],
+        last_bdu: AtomicU16::new(0),
+        timestamp_1588: AtomicU32::new(0),
+        _reserved1: [0; 8],
+    };
+}
+
+/// Buffer descriptor ring.
+#[repr(align(64))] // Alignment for optimal performance
+pub struct BDRing<D, const N: usize>([D; N]);
+
+impl<D, const N: usize> BDRing<D, N> {
+    pub const fn as_slice(&self) -> &[D] {
+        &self.0
+    }
+}
+
+pub type TxRing<const N: usize> = BDRing<tx_bd::TxBD, N>;
+pub type RxRing<const N: usize> = BDRing<rx_bd::RxBD, N>;
+
+impl<const N: usize> TxRing<N> {
+    pub const ZEROED: Self = Self([const { tx_bd::ZEROED }; N]);
+}
+
+impl<const N: usize> RxRing<N> {
+    pub const ZEROED: Self = Self([const { rx_bd::ZEROED }; N]);
+}
+
+ral_registers::register! {
+    #[doc = "Ethernet Control Register"]
+    pub ECR<u32> RW [
+        #[doc = "Ethernet MAC Reset"]
+        RESET start(0) width(1) RW {}
+        #[doc = "Ethernet Enable"]
+        ETHEREN start(1) width(1) RW {}
+        #[doc = "Magic Packet Detection Enable"]
+        MAGICEN start(2) width(1) RW {}
+        #[doc = "Sleep Mode Enable"]
+        SLEEP start(3) width(1) RW {}
+        #[doc = "EN1588 Enable"]
+        EN1588 start(4) width(1) RW {}
+        #[doc = "Selects between 10/100-Mbit/s and 1000-Mbit/s modes of operation."]
+        SPEED start(5) width(1) RW {}
+        #[doc = "Debug Enable"]
+        DBGEN start(6) width(1) RW {}
+        #[doc = "Descriptor Byte Swapping Enable"]
+        DBSWP start(8) width(1) RW {}
+        #[doc = "S-VLAN enable"]
+        SVLANEN start(9) width(1) RW {}
+        #[doc = "VLAN use second tag"]
+        VLANUSE2ND start(10) width(1) RW {}
+        #[doc = "S-VLAN double tag"]
+        SVLANDBL start(11) width(1) RW {}
+        #[doc = "Transmit clock delay"]
+        TXC_DLY start(16) width(1) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Maximum Receive Buffer Size Register - Ring 0"]
+    pub MRBR<u32> RW [
+        #[doc = "Receive buffer size in bytes"]
+        R_BUF_SIZE start(4) width(7) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Transmit Buffer Descriptor Ring 0 Start Register"]
+    pub TDSR<u32> RW []
+}
+
+pub use TDSR as TDSR1;
+pub use TDSR as TDSR2;
+
+ral_registers::register! {
+    #[doc = "Receive Descriptor Ring 0 Start Register"]
+    pub RDSR<u32> RW []
+}
+
+pub use RDSR as RDSR1;
+pub use RDSR as RDSR2;
+
+ral_registers::register! {
+    #[doc = "MII Speed Control Register"]
+    pub MSCR<u32> RW [
+        #[doc = "MII Speed"]
+        MII_SPEED start(1) width(6) RW {}
+        #[doc = "Disable Preamble"]
+        DIS_PRE start(7) width(1) RW {}
+        #[doc = "Hold time On MDIO Output"]
+        HOLDTIME start(8) width(3) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Receive Control Register"]
+    pub RCR<u32> RW [
+        #[doc = "Internal Loopback"]
+        LOOP start(0) width(1) RW {}
+        #[doc = "Disable Receive On Transmit"]
+        DRT start(1) width(1) RW {}
+        #[doc = "Media Independent Interface Mode"]
+        MII_MODE start(2) width(1) RW {}
+        #[doc = "Promiscuous Mode"]
+        PROM start(3) width(1) RW {}
+        #[doc = "Broadcast Frame Reject"]
+        BC_REJ start(4) width(1) RW {}
+        #[doc = "Flow Control Enable"]
+        FCE start(5) width(1) RW {}
+        #[doc = "RGMII Mode Enable"]
+        RGMII_EN start(6) width(1) RW {}
+        #[doc = "RMII Mode Enable"]
+        RMII_MODE start(8) width(1) RW {}
+        #[doc = "Enables 10-Mbit/s mode of the RMII or RGMII ."]
+        RMII_10T start(9) width(1) RW {}
+        #[doc = "Enable Frame Padding Remove On Receive"]
+        PADEN start(12) width(1) RW {}
+        #[doc = "Terminate/Forward Pause Frames"]
+        PAUFWD start(13) width(1) RW {}
+        #[doc = "Terminate/Forward Received CRC"]
+        CRCFWD start(14) width(1) RW {}
+        #[doc = "MAC Control Frame Enable"]
+        CFEN start(15) width(1) RW {}
+        #[doc = "Maximum Frame Length"]
+        MAX_FL start(16) width(14) RW {}
+        #[doc = "Payload Length Check Disable"]
+        NLC start(30) width(1) RW {}
+        #[doc = "Graceful Receive Stopped"]
+        GRS start(31) width(1) RO {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Transmit Control Register"]
+    pub TCR<u32> RW [
+        #[doc = "Graceful Transmit Stop"]
+        GTS start(0) width(1) RW {}
+        #[doc = "Full-Duplex Enable"]
+        FDEN start(2) width(1) RW {}
+        #[doc = "Transmit Frame Control Pause"]
+        TFC_PAUSE start(3) width(1) RW {}
+        #[doc = "Receive Frame Control Pause"]
+        RFC_PAUSE start(4) width(1) RO {}
+        #[doc = "Source MAC Address Select On Transmit"]
+        ADDSEL start(5) width(3) RW {}
+        #[doc = "Set MAC Address On Transmit"]
+        ADDINS start(8) width(1) RW {}
+        #[doc = "Forward Frame From Application With CRC"]
+        CRCFWD start(9) width(1) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Transmit FIFO Watermark Register"]
+    pub TFWR<u32> RW [
+        #[doc = "Transmit FIFO Write"]
+        TFWR start(0) width(6) RW {}
+        #[doc = "Store And Forward Enable"]
+        STRFWD start(8) width(1) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Receive FIFO Section Full Threshold"]
+    pub RSFL<u32> RW []
+}
+
+ral_registers::register! {
+    #[doc = "Receive Accelerator Function Configuration"]
+    pub RACC<u32> RW [
+        #[doc = "Enable Padding Removal For Short IP Frames"]
+        PADREM start(0) width(1) RW {}
+        #[doc = "Enable Discard Of Frames With Wrong IPv4 Header Checksum"]
+        IPDIS start(1) width(1) RW {}
+        #[doc = "Enable Discard Of Frames With Wrong Protocol Checksum"]
+        PRODIS start(2) width(1) RW {}
+        #[doc = "Enable Discard Of Frames With MAC Layer Errors"]
+        LINEDIS start(6) width(1) RW {}
+        #[doc = "RX FIFO Shift-16"]
+        SHIFT16 start(7) width(1) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Transmit Accelerator Function Configuration"]
+    pub TACC<u32> RW [
+        #[doc = "TX FIFO Shift-16"]
+        SHIFT16 start(0) width(1) RW {}
+        #[doc = "Enables insertion of IP header checksum."]
+        IPCHK start(3) width(1) RW {}
+        #[doc = "Enables insertion of protocol checksum."]
+        PROCHK start(4) width(1) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Physical Address Lower Register"]
+    pub PALR<u32> RW []
+}
+
+ral_registers::register! {
+    #[doc = "Physical Address Upper Register"]
+    pub PAUR<u32> RW []
+}
+
+ral_registers::register! {
+    #[doc = "MIB Control Register"]
+    pub MIBC<u32> RW [
+        #[doc = "MIB Clear"]
+        MIB_CLEAR start(29) width(1) RW {}
+        #[doc = "MIB Idle"]
+        MIB_IDLE start(30) width(1) RO {}
+        #[doc = "Disable MIB Logic"]
+        MIB_DIS start(31) width(1) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Transmit Descriptor Active Register - Ring 0"]
+    pub TDAR<u32> RW [
+        #[doc = "Transmit Descriptor Active"]
+        TDAR start(24) width(1) RW {}
+    ]
+}
+
+pub use TDAR as TDAR1;
+pub use TDAR as TDAR2;
+
+ral_registers::register! {
+    #[doc = "Receive Descriptor Active Register - Ring 0"]
+    pub RDAR<u32> RW [
+        #[doc = "Receive Descriptor Active"]
+        RDAR start(24) width(1) RW {}
+    ]
+}
+
+pub use RDAR as RDAR1;
+pub use RDAR as RDAR2;
+
+ral_registers::register! {
+    #[doc = "Interrupt Event Register"]
+    pub EIR<u32> RW [
+        #[doc = "Receive buffer interrupt, class 1"]
+        RXB1 start(0) width(1) RW {}
+        #[doc = "Receive frame interrupt, class 1"]
+        RXF1 start(1) width(1) RW {}
+        #[doc = "Transmit buffer interrupt, class 1"]
+        TXB1 start(2) width(1) RW {}
+        #[doc = "Transmit frame interrupt, class 1"]
+        TXF1 start(3) width(1) RW {}
+        #[doc = "Receive buffer interrupt, class 2"]
+        RXB2 start(4) width(1) RW {}
+        #[doc = "Receive frame interrupt, class 2"]
+        RXF2 start(5) width(1) RW {}
+        #[doc = "Transmit buffer interrupt, class 2"]
+        TXB2 start(6) width(1) RW {}
+        #[doc = "Transmit frame interrupt, class 2"]
+        TXF2 start(7) width(1) RW {}
+        #[doc = "RX DMA Ring 0 flush indication"]
+        RXFLUSH_0 start(12) width(1) RW {}
+        #[doc = "RX DMA Ring 1 flush indication"]
+        RXFLUSH_1 start(13) width(1) RW {}
+        #[doc = "RX DMA Ring 2 flush indication"]
+        RXFLUSH_2 start(14) width(1) RW {}
+        #[doc = "Timestamp Timer"]
+        TS_TIMER start(15) width(1) RW {}
+        #[doc = "Transmit Timestamp Available"]
+        TS_AVAIL start(16) width(1) RW {}
+        #[doc = "Node Wakeup Request Indication"]
+        WAKEUP start(17) width(1) RW {}
+        #[doc = "Payload Receive Error"]
+        PLR start(18) width(1) RW {}
+        #[doc = "Transmit FIFO Underrun"]
+        UN start(19) width(1) RW {}
+        #[doc = "Collision Retry Limit"]
+        RL start(20) width(1) RW {}
+        #[doc = "Late Collision"]
+        LC start(21) width(1) RW {}
+        #[doc = "Ethernet Bus Error"]
+        EBERR start(22) width(1) RW {}
+        #[doc = "MII Interrupt."]
+        MII start(23) width(1) RW {}
+        #[doc = "Receive Buffer Interrupt"]
+        RXB start(24) width(1) RW {}
+        #[doc = "Receive Frame Interrupt"]
+        RXF start(25) width(1) RW {}
+        #[doc = "Transmit Buffer Interrupt"]
+        TXB start(26) width(1) RW {}
+        #[doc = "Transmit Frame Interrupt"]
+        TXF start(27) width(1) RW {}
+        #[doc = "Graceful Stop Complete"]
+        GRA start(28) width(1) RW {}
+        #[doc = "Babbling Transmit Error"]
+        BABT start(29) width(1) RW {}
+        #[doc = "Babbling Receive Error"]
+        BABR start(30) width(1) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "Interrupt Mask Register"]
+    pub EIMR<u32> RW [
+        #[doc = "Receive buffer interrupt, class 1"]
+        RXB1 start(0) width(1) RW {}
+        #[doc = "Receive frame interrupt, class 1"]
+        RXF1 start(1) width(1) RW {}
+        #[doc = "Transmit buffer interrupt, class 1"]
+        TXB1 start(2) width(1) RW {}
+        #[doc = "Transmit frame interrupt, class 1"]
+        TXF1 start(3) width(1) RW {}
+        #[doc = "Receive buffer interrupt, class 2"]
+        RXB2 start(4) width(1) RW {}
+        #[doc = "Receive frame interrupt, class 2"]
+        RXF2 start(5) width(1) RW {}
+        #[doc = "Transmit buffer interrupt, class 2"]
+        TXB2 start(6) width(1) RW {}
+        #[doc = "Transmit frame interrupt, class 2"]
+        TXF2 start(7) width(1) RW {}
+        #[doc = "Corresponds to interrupt source EIR[RXFLUSH_0] and determines whether an interrupt condition can generate an interrupt"]
+        RXFLUSH_0 start(12) width(1) RW {}
+        #[doc = "Corresponds to interrupt source EIR[RXFLUSH_1] and determines whether an interrupt condition can generate an interrupt"]
+        RXFLUSH_1 start(13) width(1) RW {}
+        #[doc = "Corresponds to interrupt source EIR[RXFLUSH_2] and determines whether an interrupt condition can generate an interrupt"]
+        RXFLUSH_2 start(14) width(1) RW {}
+        #[doc = "TS_TIMER Interrupt Mask"]
+        TS_TIMER start(15) width(1) RW {}
+        #[doc = "TS_AVAIL Interrupt Mask"]
+        TS_AVAIL start(16) width(1) RW {}
+        #[doc = "WAKEUP Interrupt Mask"]
+        WAKEUP start(17) width(1) RW {}
+        #[doc = "PLR Interrupt Mask"]
+        PLR start(18) width(1) RW {}
+        #[doc = "UN Interrupt Mask"]
+        UN start(19) width(1) RW {}
+        #[doc = "RL Interrupt Mask"]
+        RL start(20) width(1) RW {}
+        #[doc = "LC Interrupt Mask"]
+        LC start(21) width(1) RW {}
+        #[doc = "EBERR Interrupt Mask"]
+        EBERR start(22) width(1) RW {}
+        #[doc = "MII Interrupt Mask"]
+        MII start(23) width(1) RW {}
+        #[doc = "RXB Interrupt Mask"]
+        RXB start(24) width(1) RW {}
+        #[doc = "RXF Interrupt Mask"]
+        RXF start(25) width(1) RW {}
+        #[doc = "TXB Interrupt Mask"]
+        TXB start(26) width(1) RW {}
+        #[doc = "TXF Interrupt Mask"]
+        TXF start(27) width(1) RW {}
+        #[doc = "GRA Interrupt Mask"]
+        GRA start(28) width(1) RW {}
+        #[doc = "BABT Interrupt Mask"]
+        BABT start(29) width(1) RW {}
+        #[doc = "BABR Interrupt Mask"]
+        BABR start(30) width(1) RW {}
+    ]
+}
+
+ral_registers::register! {
+    #[doc = "MII Management Frame Register"]
+    pub MMFR<u32> RW [
+        #[doc = "Management Frame Data"]
+        DATA start(0) width(16) RW {}
+        #[doc = "Turn Around"]
+        TA start(16) width(2) RW {}
+        #[doc = "Register Address"]
+        RA start(18) width(5) RW {}
+        #[doc = "PHY Address"]
+        PA start(23) width(5) RW {}
+        #[doc = "Operation Code"]
+        OP start(28) width(2) RW {}
+        #[doc = "Start Of Frame Delimiter"]
+        ST start(30) width(2) RW {}
+    ]
+}
+
+#[cfg(test)]
+mod tests {
+    use super::RegisterBlock;
+    use core::mem::offset_of;
+
+    #[test]
+    fn layout() {
+        assert_eq!(offset_of!(RegisterBlock, EIR), 0x04);
+        assert_eq!(offset_of!(RegisterBlock, MMFR), 0x40);
+        assert_eq!(offset_of!(RegisterBlock, MSCR), 0x44);
+        assert_eq!(offset_of!(RegisterBlock, TACC), 0x1C0);
+        assert_eq!(offset_of!(RegisterBlock, RACC), 0x1C4);
+    }
+}