1 files changed, 85 insertions, 0 deletions
diff --git a/drivers/ccm-10xx/src/ral/ccm.rs b/drivers/ccm-10xx/src/ral/ccm.rs
new file mode 100644
index 0000000..e8033ac
--- /dev/null
+++ b/drivers/ccm-10xx/src/ral/ccm.rs
@@ -0,0 +1,85 @@
+use ral_registers::{Instance, register};
+
+#[repr(C)]
+#[allow(non_snake_case)]
+pub struct RegisterBlock {
+    pub CCR: u32,
+    _reserved0: [u8; 0x04],
+    pub CSR: u32,
+    pub CCSR: u32,
+    pub CACRR: u32,
+    pub CBCDR: u32,
+    pub CBCMR: u32,
+    pub CSCMR1: u32,
+    pub CSCMR2: u32,
+    pub CSCDR1: u32,
+    pub CS1CDR: u32,
+    pub CS2CDR: u32,
+    pub CDCDR: u32,
+    _reserved1: [u8; 0x04],
+    pub CSCDR2: u32,
+    pub CSCDR3: u32,
+    _reserved2: [u8; 0x08],
+    pub CDHIPR: u32,
+    _reserved3: [u8; 0x08],
+    pub CLPCR: u32,
+    pub CISR: u32,
+    pub CIMR: u32,
+    pub CCOSR: u32,
+    pub CGPR: u32,
+    pub CCGR: [u32; 8],
+    pub CMEOR: u32,
+}
+
+/// A CCM instance.
+pub type CCM = Instance<RegisterBlock>;
+
+register!(pub(crate) CACRR<u32> RW [
+    ARM_PODF        start(0) width(3) RW {}
+]);
+
+register!(pub(crate) CSCMR1<u32> RW [
+    FLEXSPI_CLK_SRC start(31) width(1) RW {}
+    FLEXSPI_CLK_SEL start(29) width(2) RW {}
+    FLEXSPI_PODF    start(23) width(3) RW {}
+    PERCLK_PODF     start(0) width(6) RW {}
+    PERCLK_CLK_SEL  start(6) width(1) RW {}
+]);
+
+register!(pub(crate) CBCDR<u32> RW [
+    PERIPH_CLK2_PODF start(27) width(3) RW {}
+    PERIPH_CLK_SEL  start(25) width(1) RW {}
+    AHB_PODF        start(10) width(3) RW {}
+    IPG_PODF        start(8) width(2) RW {}
+]);
+
+register!(pub(crate) CLPCR<u32> RW [
+    LPM             start(0) width(2) RW {
+        RUN = 0,
+        WAIT = 1,
+        STOP = 2,
+    }
+]);
+
+register!(pub(crate) CSCDR1<u32> RW [
+    UART_CLK_PODF   start(0) width(6) RW {}
+    /// Reduced to 1 bit, which is supported across
+    /// all chip variants.
+    UART_CLK_SEL    start(6) width(1) RW {}
+]);
+
+register!(pub(crate) CSCDR2<u32> RW [
+    LPI2C_CLK_PODF  start(19) width(6) RW {}
+    LPI2C_CLK_SEL   start(18) width(1) RW {}
+]);
+
+register!(pub(crate) CBCMR<u32> RW [
+    /// Four bits wide on the 1010.
+    LPSPI_PODF      start(26) width(3) RW {}
+    PRE_PERIPH_CLK_SEL start(18) width(2) RW {}
+    PERIPH_CLK2_SEL start(12) width(2) RW {}
+    LPSPI_CLK_SEL   start(4)  width(2) RW {}
+]);
+
+register!(pub(crate) CCGR<u32> RW []);
+register!(pub(crate) CDHIPR<u32> RO []);