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-rw-r--r--drivers/iomuxc-11xx/src/lib.rs475
1 files changed, 475 insertions, 0 deletions
diff --git a/drivers/iomuxc-11xx/src/lib.rs b/drivers/iomuxc-11xx/src/lib.rs
new file mode 100644
index 0000000..54f0c17
--- /dev/null
+++ b/drivers/iomuxc-11xx/src/lib.rs
@@ -0,0 +1,475 @@
+#![no_std]
+
+pub mod iomuxc_gpr {
+ #[repr(C)]
+ #[allow(non_snake_case)]
+ pub struct RegisterBlock {
+ pub GPR: [u32; 76],
+ }
+
+ ral_registers::register!(pub GPR<u32> RW []);
+}
+
+pub mod iomuxc {
+ #[repr(C)]
+ #[allow(non_snake_case)]
+ pub struct RegisterBlock {
+ _reserved: [u8; 16],
+ pub SW_MUX_CTL_PAD: PadLayout,
+ pub SW_PAD_CTL_PAD: PadLayout,
+ pub SELECT_INPUT: [u32; 160],
+ }
+
+ #[doc(hidden)]
+ #[repr(C)]
+ #[allow(non_snake_case)]
+ pub struct PadLayout {
+ pub GPIO_EMC_B1: [u32; 42],
+ pub GPIO_EMC_B2: [u32; 21],
+ pub GPIO_AD: [u32; 36],
+ pub GPIO_SD_B1: [u32; 6],
+ pub GPIO_SD_B2: [u32; 12],
+ pub GPIO_DISP_B1: [u32; 12],
+ pub GPIO_DISP_B2: [u32; 16],
+ }
+
+ const _: () = assert!(size_of::<PadLayout>() == size_of::<[u32; 145]>());
+
+ #[allow(non_snake_case)]
+ pub mod SW_PAD_CTL_PAD {
+ #[doc(inline)]
+ pub use super::PadLayout as RegisterBlock;
+
+ ral_registers::register! {
+ #[doc(hidden)]
+ pub v1<u32> RW [
+ #[doc = "PDRV Field"]
+ PDRV start(1) width(1) RW {
+ HIGH = 0
+ NORMAL = 0x1,
+ }
+ #[doc = "Pull Down Pull Up Field"]
+ PULL start(2) width(2) RW {
+ PULL_UP = 0x1,
+ PULL_DOWN = 0x2,
+ NO_PULL = 0x3,
+ }
+ #[doc = "Open Drain Field"]
+ ODE start(4) width(1) RW {}
+ #[doc = "Domain write protection"]
+ DWP start(28) width(2) RW {}
+ #[doc = "Domain write protection lock"]
+ DWP_LOCK start(30) width(2) RW {}
+ ]
+ }
+
+ ral_registers::register! {
+ #[doc(hidden)]
+ pub v2<u32> RW [
+ #[doc = "Slew Rate Field"]
+ SRE start(0) width(1) RW {
+ SLOW = 0,
+ FAST = 0x1,
+ }
+ #[doc = "Drive Strength Field"]
+ DSE start(1) width(1) RW {
+ NORMAL = 0,
+ HIGH = 0x1,
+ }
+ #[doc = "Pull / Keep Select Field"]
+ PUE start(2) width(1) RW {}
+ #[doc = "Pull Up / Down Config. Field"]
+ PUS start(3) width(1) RW {
+ PULL_DOWN = 0,
+ PULL_UP = 0x1,
+ }
+ #[doc = "Open Drain Field"]
+ ODE start(4) width(1) RW {}
+ #[doc = "Domain write protection"]
+ DWP start(28) width(2) RW {}
+ #[doc = "Domain write protection lock"]
+ DWP_LOCK start(30) width(2) RW {}
+ ]
+ }
+
+ #[doc(inline)]
+ pub use v1 as GPIO_EMC_B1;
+ #[doc(inline)]
+ pub use v1 as GPIO_EMC_B2;
+ #[doc(inline)]
+ pub use v1 as GPIO_SD_B1;
+ #[doc(inline)]
+ pub use v1 as GPIO_SD_B2;
+ #[doc(inline)]
+ pub use v1 as GPIO_DISP_B1;
+
+ #[doc(inline)]
+ pub use v2 as GPIO_AD;
+ #[doc(inline)]
+ pub use v2 as GPIO_DISP_B2;
+ }
+
+ #[allow(non_snake_case)]
+ pub mod SW_MUX_CTL_PAD {
+ #[doc(inline)]
+ pub use super::PadLayout as RegisterBlock;
+
+ ral_registers::register! {
+ #[doc(hidden)]
+ pub common<u32> RW [
+ #[doc = "MUX Mode Select Field."]
+ MUX_MODE start(0) width(4) RW {}
+ #[doc = "Software Input On Field."]
+ SION start(4) width(1) RW {}
+ ]
+ }
+
+ #[doc(inline)]
+ pub use common as GPIO_EMC_B1;
+ #[doc(inline)]
+ pub use common as GPIO_EMC_B2;
+ #[doc(inline)]
+ pub use common as GPIO_SD_B1;
+ #[doc(inline)]
+ pub use common as GPIO_SD_B2;
+ #[doc(inline)]
+ pub use common as GPIO_DISP_B1;
+ #[doc(inline)]
+ pub use common as GPIO_DISP_B2;
+ #[doc(inline)]
+ pub use common as GPIO_AD;
+ }
+
+ pub mod select_input {
+ pub const FLEXCAN1_RX: usize = 0;
+ pub const FLEXCAN2_RX: usize = 1;
+ pub const CCM_ENET_QOS_REF_CLK: usize = 2;
+ pub const CCM_ENET_QOS_TX_CLK: usize = 3;
+ pub const ENET_IPG_CLK_RMII: usize = 4;
+ pub const ENET_MAC0_MDIO: usize = 5;
+ pub const ENET_MAC0_RXDATA_0: usize = 6;
+ pub const ENET_MAC0_RXDATA_1: usize = 7;
+ pub const ENET_MAC0_RXEN: usize = 8;
+ pub const ENET_MAC0_RXERR: usize = 9;
+ pub const ENET_MAC0_TXCLK: usize = 10;
+ pub const ENET_1G_IPG_CLK_RMII: usize = 11;
+ pub const ENET_1G_MAC0_MDIO: usize = 12;
+ pub const ENET_1G_MAC0_RXCLK: usize = 13;
+ pub const ENET_1G_MAC0_RXDATA_0: usize = 14;
+ pub const ENET_1G_MAC0_RXDATA_1: usize = 15;
+ pub const ENET_1G_MAC0_RXDATA_2: usize = 16;
+ pub const ENET_1G_MAC0_RXDATA_3: usize = 17;
+ pub const ENET_1G_MAC0_RXEN: usize = 18;
+ pub const ENET_1G_MAC0_RXERR: usize = 19;
+ pub const ENET_1G_MAC0_TXCLK: usize = 20;
+ pub const ENET_QOS_GMII_MDI_I: usize = 21;
+ pub const ENET_QOS_PHY_RXD_I_0: usize = 22;
+ pub const ENET_QOS_PHY_RXD_I_1: usize = 23;
+ pub const ENET_QOS_PHY_RXDV_I: usize = 24;
+ pub const ENET_QOS_PHY_RXER_I: usize = 25;
+ pub const FLEXPWM1_PWMA_0: usize = 26;
+ pub const FLEXPWM1_PWMA_1: usize = 27;
+ pub const FLEXPWM1_PWMA_2: usize = 28;
+ pub const FLEXPWM1_PWMB_0: usize = 29;
+ pub const FLEXPWM1_PWMB_1: usize = 30;
+ pub const FLEXPWM1_PWMB_2: usize = 31;
+ pub const FLEXPWM2_PWMA_0: usize = 32;
+ pub const FLEXPWM2_PWMA_1: usize = 33;
+ pub const FLEXPWM2_PWMA_2: usize = 34;
+ pub const FLEXPWM2_PWMB_0: usize = 35;
+ pub const FLEXPWM2_PWMB_1: usize = 36;
+ pub const FLEXPWM2_PWMB_2: usize = 37;
+ pub const FLEXPWM3_PWMA_0: usize = 38;
+ pub const FLEXPWM3_PWMA_1: usize = 39;
+ pub const FLEXPWM3_PWMA_2: usize = 40;
+ pub const FLEXPWM3_PWMA_3: usize = 41;
+ pub const FLEXPWM3_PWMB_0: usize = 42;
+ pub const FLEXPWM3_PWMB_1: usize = 43;
+ pub const FLEXPWM3_PWMB_2: usize = 44;
+ pub const FLEXPWM3_PWMB_3: usize = 45;
+ pub const FLEXSPI1_I_DQS_FA: usize = 46;
+ pub const FLEXSPI1_I_IO_FA_0: usize = 47;
+ pub const FLEXSPI1_I_IO_FA_1: usize = 48;
+ pub const FLEXSPI1_I_IO_FA_2: usize = 49;
+ pub const FLEXSPI1_I_IO_FA_3: usize = 50;
+ pub const FLEXSPI1_I_IO_FB_0: usize = 51;
+ pub const FLEXSPI1_I_IO_FB_1: usize = 52;
+ pub const FLEXSPI1_I_IO_FB_2: usize = 53;
+ pub const FLEXSPI1_I_IO_FB_3: usize = 54;
+ pub const FLEXSPI1_I_SCK_FA: usize = 55;
+ pub const FLEXSPI1_I_SCK_FB: usize = 56;
+ pub const FLEXSPI2_I_IO_FA_0: usize = 57;
+ pub const FLEXSPI2_I_IO_FA_1: usize = 58;
+ pub const FLEXSPI2_I_IO_FA_2: usize = 59;
+ pub const FLEXSPI2_I_IO_FA_3: usize = 60;
+ pub const FLEXSPI2_I_SCK_FA: usize = 61;
+ pub const GPT3_CAPIN1: usize = 62;
+ pub const GPT3_CAPIN2: usize = 63;
+ pub const GPT3_CLKIN: usize = 64;
+ pub const KPP_COL_6: usize = 65;
+ pub const KPP_COL_7: usize = 66;
+ pub const KPP_ROW_6: usize = 67;
+ pub const KPP_ROW_7: usize = 68;
+ pub const LPI2C1_LPI2C_SCL: usize = 69;
+ pub const LPI2C1_LPI2C_SDA: usize = 70;
+ pub const LPI2C2_LPI2C_SCL: usize = 71;
+ pub const LPI2C2_LPI2C_SDA: usize = 72;
+ pub const LPI2C3_LPI2C_SCL: usize = 73;
+ pub const LPI2C3_LPI2C_SDA: usize = 74;
+ pub const LPI2C4_LPI2C_SCL: usize = 75;
+ pub const LPI2C4_LPI2C_SDA: usize = 76;
+ pub const LPSPI1_LPSPI_PCS_0: usize = 77;
+ pub const LPSPI1_LPSPI_SCK: usize = 78;
+ pub const LPSPI1_LPSPI_SDI: usize = 79;
+ pub const LPSPI1_LPSPI_SDO: usize = 80;
+ pub const LPSPI2_LPSPI_PCS_0: usize = 81;
+ pub const LPSPI2_LPSPI_PCS_1: usize = 82;
+ pub const LPSPI2_LPSPI_SCK: usize = 83;
+ pub const LPSPI2_LPSPI_SDI: usize = 84;
+ pub const LPSPI2_LPSPI_SDO: usize = 85;
+ pub const LPSPI3_LPSPI_PCS_0: usize = 86;
+ pub const LPSPI3_LPSPI_PCS_1: usize = 87;
+ pub const LPSPI3_LPSPI_PCS_2: usize = 88;
+ pub const LPSPI3_LPSPI_PCS_3: usize = 89;
+ pub const LPSPI3_LPSPI_SCK: usize = 90;
+ pub const LPSPI3_LPSPI_SDI: usize = 91;
+ pub const LPSPI3_LPSPI_SDO: usize = 92;
+ pub const LPSPI4_LPSPI_PCS_0: usize = 93;
+ pub const LPSPI4_LPSPI_SCK: usize = 94;
+ pub const LPSPI4_LPSPI_SDI: usize = 95;
+ pub const LPSPI4_LPSPI_SDO: usize = 96;
+ pub const LPUART1_LPUART_RXD: usize = 97;
+ pub const LPUART1_LPUART_TXD: usize = 98;
+ pub const LPUART10_LPUART_RXD: usize = 99;
+ pub const LPUART10_LPUART_TXD: usize = 100;
+ pub const LPUART7_LPUART_RXD: usize = 101;
+ pub const LPUART7_LPUART_TXD: usize = 102;
+ pub const LPUART8_LPUART_RXD: usize = 103;
+ pub const LPUART8_LPUART_TXD: usize = 104;
+ pub const QTIMER1_TMR0_INPUT: usize = 105;
+ pub const QTIMER1_TMR1_INPUT: usize = 106;
+ pub const QTIMER1_TMR2_INPUT: usize = 107;
+ pub const QTIMER2_TMR0_INPUT: usize = 108;
+ pub const QTIMER2_TMR1_INPUT: usize = 109;
+ pub const QTIMER2_TMR2_INPUT: usize = 110;
+ pub const QTIMER3_TMR0_INPUT: usize = 111;
+ pub const QTIMER3_TMR1_INPUT: usize = 112;
+ pub const QTIMER3_TMR2_INPUT: usize = 113;
+ pub const QTIMER4_TMR0_INPUT: usize = 114;
+ pub const QTIMER4_TMR1_INPUT: usize = 115;
+ pub const QTIMER4_TMR2_INPUT: usize = 116;
+ pub const SAI1_IPG_CLK_SAI_MCLK: usize = 117;
+ pub const SAI1_SAI_RXBCLK: usize = 118;
+ pub const SAI1_SAI_RXDATA_0: usize = 119;
+ pub const SAI1_SAI_RXSYNC: usize = 120;
+ pub const SAI1_SAI_TXBCLK: usize = 121;
+ pub const SAI1_SAI_TXSYNC: usize = 122;
+ pub const EMVSIM1_SIO: usize = 129;
+ pub const EMVSIM1_IPP_SIMPD: usize = 130;
+ pub const EMVSIM1_POWER_FAIL: usize = 131;
+ pub const EMVSIM2_SIO: usize = 132;
+ pub const EMVSIM2_IPP_SIMPD: usize = 133;
+ pub const EMVSIM2_POWER_FAIL: usize = 134;
+ pub const SPDIF_SPDIF_IN1: usize = 135;
+ pub const USB_OTG2_OC: usize = 136;
+ pub const USB_OTG_OC: usize = 137;
+ pub const USBPHY1_USB_ID: usize = 138;
+ pub const USBPHY2_USB_ID: usize = 139;
+ pub const USDHC1_IPP_CARD_DET: usize = 140;
+ pub const USDHC1_IPP_WP_ON: usize = 141;
+ pub const USDHC2_IPP_CARD_DET: usize = 142;
+ pub const USDHC2_IPP_WP_ON: usize = 143;
+ pub const XBAR1_IN_20: usize = 144;
+ pub const XBAR1_IN_21: usize = 145;
+ pub const XBAR1_IN_22: usize = 146;
+ pub const XBAR1_IN_23: usize = 147;
+ pub const XBAR1_IN_24: usize = 148;
+ pub const XBAR1_IN_25: usize = 149;
+ pub const XBAR1_IN_26: usize = 150;
+ pub const XBAR1_IN_27: usize = 151;
+ pub const XBAR1_IN_28: usize = 152;
+ pub const XBAR1_IN_29: usize = 153;
+ pub const XBAR1_IN_30: usize = 154;
+ pub const XBAR1_IN_31: usize = 155;
+ pub const XBAR1_IN_32: usize = 156;
+ pub const XBAR1_IN_33: usize = 157;
+ pub const XBAR1_IN_34: usize = 158;
+ pub const XBAR1_IN_35: usize = 159;
+ }
+
+ ral_registers::register! {
+ pub SELECT_INPUT<u32> RW []
+ }
+}
+
+pub mod iomuxc_lpsr {
+ #[repr(C)]
+ #[allow(non_snake_case)]
+ pub struct RegisterBlock {
+ pub SW_MUX_CTL_PAD: [u32; 16],
+ pub SW_PAD_CTL_PAD: [u32; 16],
+ pub SELECT_INPUT: [u32; 24],
+ }
+
+ #[doc(inline)]
+ pub use super::iomuxc::SW_MUX_CTL_PAD::common as SW_MUX_CTL_PAD;
+
+ ral_registers::register! {
+ pub SW_PAD_CTL_PAD<u32> RW [
+ #[doc = "Slew Rate Field"]
+ SRE start(0) width(1) RW {
+ SLOW = 0,
+ FAST = 0x1,
+ }
+ #[doc = "Drive Strength Field"]
+ DSE start(1) width(1) RW {
+ NORMAL = 0,
+ HIGH = 0x1,
+ }
+ #[doc = "Pull / Keep Select Field"]
+ PUE start(2) width(1) RW {}
+ #[doc = "Pull Up / Down Config. Field"]
+ PUS start(3) width(1) RW {
+ PULL_DOWN = 0,
+ PULL_UP = 0x1,
+ }
+ #[doc = "Open Drain LPSR Field"]
+ ODE start(5) width(1) RW {}
+ #[doc = "Domain write protection"]
+ DWP start(28) width(2) RW {}
+ #[doc = "Domain write protection lock"]
+ DWP_LOCK start(30) width(2) RW {}
+ ]
+ }
+
+ pub mod select_input {
+ pub const CAN3_IPP_IND_CANRX: usize = 0;
+ pub const LPI2C5_IPP_IND_LPI2C_SCL: usize = 1;
+ pub const LPI2C5_IPP_IND_LPI2C_SDA: usize = 2;
+ pub const LPI2C6_IPP_IND_LPI2C_SCL: usize = 3;
+ pub const LPI2C6_IPP_IND_LPI2C_SDA: usize = 4;
+ pub const LPSPI5_IPP_IND_LPSPI_PCS_0: usize = 5;
+ pub const LPSPI5_IPP_IND_LPSPI_SCK: usize = 6;
+ pub const LPSPI5_IPP_IND_LPSPI_SDI: usize = 7;
+ pub const LPSPI5_IPP_IND_LPSPI_SDO: usize = 8;
+ pub const LPUART11_IPP_IND_LPUART_RXD: usize = 9;
+ pub const LPUART11_IPP_IND_LPUART_TXD: usize = 10;
+ pub const LPUART12_IPP_IND_LPUART_RXD: usize = 11;
+ pub const LPUART12_IPP_IND_LPUART_TXD: usize = 12;
+ pub const MIC_IPP_IND_MIC_PDM_BITSTREAM_0: usize = 13;
+ pub const MIC_IPP_IND_MIC_PDM_BITSTREAM_1: usize = 14;
+ pub const MIC_IPP_IND_MIC_PDM_BITSTREAM_2: usize = 15;
+ pub const MIC_IPP_IND_MIC_PDM_BITSTREAM_3: usize = 16;
+ pub const NMI_GLUE_IPP_IND_NMI: usize = 17;
+ pub const SAI4_IPG_CLK_SAI_MCLK: usize = 18;
+ pub const SAI4_IPP_IND_SAI_RXBCLK: usize = 19;
+ pub const SAI4_IPP_IND_SAI_RXDATA_0: usize = 20;
+ pub const SAI4_IPP_IND_SAI_RXSYNC: usize = 21;
+ pub const SAI4_IPP_IND_SAI_TXBCLK: usize = 22;
+ pub const SAI4_IPP_IND_SAI_TXSYNC: usize = 23;
+ }
+
+ ral_registers::register! {
+ pub SELECT_INPUT<u32> RW []
+ }
+}
+
+pub mod iomuxc_aon {
+ #[repr(C)]
+ #[allow(non_snake_case)]
+ pub struct RegisterBlock {
+ pub SW_MUX_CTL_PAD: [u32; 29],
+ pub SW_PAD_CTL_PAD: [u32; 29],
+ pub SELECT_INPUT: [u32; 39],
+ }
+
+ #[doc(inline)]
+ pub use super::iomuxc::SW_MUX_CTL_PAD::common as SW_MUX_CTL_PAD;
+
+ ral_registers::register! {
+ pub SW_PAD_CTL_PAD<u32> RW [
+ #[doc = "Slew Rate Field"]
+ SRE start(0) width(1) RW {
+ FAST = 0,
+ SLOW = 0x1,
+ }
+ #[doc = "Drive Strength Field"]
+ DSE start(1) width(1) RW {
+ NORMAL = 0,
+ HIGH = 0x1,
+ }
+ #[doc = "Pull / Keep Select Field"]
+ PUE start(2) width(1) RW {}
+ #[doc = "Pull Up / Down Config. Field"]
+ PUS start(3) width(1) RW {
+ PULL_DOWN = 0,
+ PULL_UP = 0x1,
+ }
+ #[doc = "Open Drain Field"]
+ ODE start(4) width(1) RW {}
+ #[doc = "Domain write protection"]
+ DWP start(24) width(4) RW {}
+ #[doc = "Domain write protection lock"]
+ DWP_LOCK start(28) width(4) RW {}
+ ]
+ }
+
+ pub mod select_input {
+ pub const I3C1_PIN_SCL_IN: usize = 0;
+ pub const I3C1_PIN_SDA_IN: usize = 1;
+ pub const LPI2C1_IPP_IND_LPI2C_SCL: usize = 2;
+ pub const LPI2C1_IPP_IND_LPI2C_SDA: usize = 3;
+ pub const LPI2C2_IPP_IND_LPI2C_SCL: usize = 4;
+ pub const LPI2C2_IPP_IND_LPI2C_SDA: usize = 5;
+ pub const LPSPI1_IPP_IND_LPSPI_PCS_0: usize = 6;
+ pub const LPSPI1_IPP_IND_LPSPI_PCS_1: usize = 7;
+ pub const LPSPI1_IPP_IND_LPSPI_SCK: usize = 8;
+ pub const LPSPI1_IPP_IND_LPSPI_SDI: usize = 9;
+ pub const LPSPI1_IPP_IND_LPSPI_SDO: usize = 10;
+ pub const LPSPI2_IPP_IND_LPSPI_PCS_0: usize = 11;
+ pub const LPSPI2_IPP_IND_LPSPI_PCS_1: usize = 12;
+ pub const LPSPI2_IPP_IND_LPSPI_PCS_3: usize = 13;
+ pub const LPSPI2_IPP_IND_LPSPI_SCK: usize = 14;
+ pub const LPSPI2_IPP_IND_LPSPI_SDI: usize = 15;
+ pub const LPSPI2_IPP_IND_LPSPI_SDO: usize = 16;
+ pub const LPTMR1_IPP_IND_LPTIMER_1: usize = 17;
+ pub const LPTMR1_IPP_IND_LPTIMER_2: usize = 18;
+ pub const LPTMR1_IPP_IND_LPTIMER_3: usize = 19;
+ pub const LPUART1_IPP_IND_LPUART_CTS_N: usize = 20;
+ pub const LPUART1_IPP_IND_LPUART_DCD_N: usize = 21;
+ pub const LPUART1_IPP_IND_LPUART_DSR_N: usize = 22;
+ pub const LPUART12_IPP_IND_LPUART_CTS_N: usize = 23;
+ pub const LPUART12_IPP_IND_LPUART_RXD: usize = 24;
+ pub const LPUART12_IPP_IND_LPUART_TXD: usize = 25;
+ pub const LPUART2_IPP_IND_LPUART_CTS_N: usize = 26;
+ pub const LPUART2_IPP_IND_LPUART_RXD: usize = 27;
+ pub const LPUART2_IPP_IND_LPUART_TXD: usize = 28;
+ pub const LPUART7_IPP_IND_LPUART_CTS_N: usize = 29;
+ pub const LPUART7_IPP_IND_LPUART_RXD: usize = 30;
+ pub const LPUART7_IPP_IND_LPUART_TXD: usize = 31;
+ pub const SAI1_IPG_CLK_SAI_MCLK: usize = 32;
+ pub const SAI1_IPP_IND_SAI_RXBCLK: usize = 33;
+ pub const SAI1_IPP_IND_SAI_RXDATA_0: usize = 34;
+ pub const SAI1_IPP_IND_SAI_RXDATA_1: usize = 35;
+ pub const SAI1_IPP_IND_SAI_RXSYNC: usize = 36;
+ pub const SAI1_IPP_IND_SAI_TXBCLK: usize = 37;
+ pub const SAI1_IPP_IND_SAI_TXSYNC: usize = 38;
+ }
+
+ ral_registers::register! {
+ pub SELECT_INPUT<u32> RW []
+ }
+}
+
+#[cfg(test)]
+mod tests {
+ use core::mem::offset_of;
+
+ use super::iomuxc::RegisterBlock as Iomuxc;
+
+ #[test]
+ fn iomuxc_layout() {
+ assert_eq!(offset_of!(Iomuxc, SW_PAD_CTL_PAD.GPIO_AD), 0x350);
+ assert_eq!(offset_of!(Iomuxc, SELECT_INPUT), 0x498);
+ }
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-26 18:51:26 +0000