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//! I/O multiplexing and configuration.
pub type RegisterBlock = imxrt_drivers_iomuxc_10xx::iomuxc::RegisterBlock<20, 124, 231>;
pub type Instance = ral_registers::Instance<RegisterBlock>;
pub use imxrt_drivers_iomuxc_10xx::iomuxc::{SELECT_INPUT, SW_MUX_CTL_PAD, SW_PAD_CTL_PAD};
/// Indices for `sw_[pad|mux]_ctl_pad` registers.
pub mod pad {
pub const GPIO_EMC_00: usize = 0;
pub const GPIO_EMC_01: usize = 1;
pub const GPIO_EMC_02: usize = 2;
pub const GPIO_EMC_03: usize = 3;
pub const GPIO_EMC_04: usize = 4;
pub const GPIO_EMC_05: usize = 5;
pub const GPIO_EMC_06: usize = 6;
pub const GPIO_EMC_07: usize = 7;
pub const GPIO_EMC_08: usize = 8;
pub const GPIO_EMC_09: usize = 9;
pub const GPIO_EMC_10: usize = 10;
pub const GPIO_EMC_11: usize = 11;
pub const GPIO_EMC_12: usize = 12;
pub const GPIO_EMC_13: usize = 13;
pub const GPIO_EMC_14: usize = 14;
pub const GPIO_EMC_15: usize = 15;
pub const GPIO_EMC_16: usize = 16;
pub const GPIO_EMC_17: usize = 17;
pub const GPIO_EMC_18: usize = 18;
pub const GPIO_EMC_19: usize = 19;
pub const GPIO_EMC_20: usize = 20;
pub const GPIO_EMC_21: usize = 21;
pub const GPIO_EMC_22: usize = 22;
pub const GPIO_EMC_23: usize = 23;
pub const GPIO_EMC_24: usize = 24;
pub const GPIO_EMC_25: usize = 25;
pub const GPIO_EMC_26: usize = 26;
pub const GPIO_EMC_27: usize = 27;
pub const GPIO_EMC_28: usize = 28;
pub const GPIO_EMC_29: usize = 29;
pub const GPIO_EMC_30: usize = 30;
pub const GPIO_EMC_31: usize = 31;
pub const GPIO_EMC_32: usize = 32;
pub const GPIO_EMC_33: usize = 33;
pub const GPIO_EMC_34: usize = 34;
pub const GPIO_EMC_35: usize = 35;
pub const GPIO_EMC_36: usize = 36;
pub const GPIO_EMC_37: usize = 37;
pub const GPIO_EMC_38: usize = 38;
pub const GPIO_EMC_39: usize = 39;
pub const GPIO_EMC_40: usize = 40;
pub const GPIO_EMC_41: usize = 41;
pub const GPIO_AD_B0_04: usize = 46;
pub const GPIO_AD_B0_05: usize = 47;
pub const GPIO_AD_B0_06: usize = 48;
pub const GPIO_AD_B0_07: usize = 49;
pub const GPIO_AD_B0_08: usize = 50;
pub const GPIO_AD_B0_09: usize = 51;
pub const GPIO_AD_B0_10: usize = 52;
pub const GPIO_AD_B0_11: usize = 53;
pub const GPIO_AD_B0_12: usize = 54;
pub const GPIO_AD_B0_13: usize = 55;
pub const GPIO_AD_B0_14: usize = 56;
pub const GPIO_AD_B0_15: usize = 57;
pub const GPIO_AD_B1_00: usize = 58;
pub const GPIO_AD_B1_01: usize = 59;
pub const GPIO_AD_B1_02: usize = 60;
pub const GPIO_AD_B1_03: usize = 61;
pub const GPIO_AD_B1_04: usize = 62;
pub const GPIO_AD_B1_05: usize = 63;
pub const GPIO_AD_B1_06: usize = 64;
pub const GPIO_AD_B1_07: usize = 65;
pub const GPIO_B0_00: usize = 74;
pub const GPIO_B0_01: usize = 75;
pub const GPIO_B0_02: usize = 76;
pub const GPIO_B0_03: usize = 77;
pub const GPIO_B0_04: usize = 78;
pub const GPIO_B0_05: usize = 79;
pub const GPIO_B0_06: usize = 80;
pub const GPIO_B0_07: usize = 81;
pub const GPIO_B0_08: usize = 82;
pub const GPIO_B0_09: usize = 83;
pub const GPIO_B0_10: usize = 84;
pub const GPIO_B0_11: usize = 85;
pub const GPIO_B0_12: usize = 86;
pub const GPIO_B0_13: usize = 87;
pub const GPIO_B0_14: usize = 88;
pub const GPIO_B0_15: usize = 89;
pub const GPIO_B1_00: usize = 90;
pub const GPIO_B1_01: usize = 91;
pub const GPIO_B1_02: usize = 92;
pub const GPIO_B1_03: usize = 93;
pub const GPIO_B1_04: usize = 94;
pub const GPIO_B1_05: usize = 95;
pub const GPIO_B1_06: usize = 96;
pub const GPIO_B1_07: usize = 97;
pub const GPIO_B1_08: usize = 98;
pub const GPIO_B1_09: usize = 99;
pub const GPIO_B1_10: usize = 100;
pub const GPIO_B1_11: usize = 101;
pub const GPIO_B1_12: usize = 102;
pub const GPIO_B1_13: usize = 103;
pub const GPIO_B1_14: usize = 104;
pub const GPIO_B1_15: usize = 105;
pub const GPIO_SD_B0_00: usize = 106;
pub const GPIO_SD_B0_01: usize = 107;
pub const GPIO_SD_B0_02: usize = 108;
pub const GPIO_SD_B0_03: usize = 109;
pub const GPIO_SD_B0_04: usize = 110;
pub const GPIO_SD_B0_05: usize = 111;
pub const GPIO_SD_B1_00: usize = 112;
pub const GPIO_SD_B1_01: usize = 113;
pub const GPIO_SD_B1_02: usize = 114;
pub const GPIO_SD_B1_03: usize = 115;
pub const GPIO_SD_B1_04: usize = 116;
pub const GPIO_SD_B1_05: usize = 117;
pub const GPIO_SD_B1_06: usize = 118;
pub const GPIO_SD_B1_07: usize = 119;
pub const GPIO_SD_B1_08: usize = 120;
pub const GPIO_SD_B1_09: usize = 121;
pub const GPIO_SD_B1_10: usize = 122;
pub const GPIO_SD_B1_11: usize = 123;
}
/// Indices for `select_input` registers.
pub mod select_input {
pub const ANATOP_USB_OTG1_ID: usize = 0;
pub const CCM_PMIC_READY: usize = 2;
pub const ENET_IPG_CLK_RMII: usize = 14;
pub const ENET_MDIO: usize = 15;
pub const ENET0_RXDATA: usize = 16;
pub const ENET1_RXDATA: usize = 17;
pub const ENET_RXEN: usize = 18;
pub const ENET_RXERR: usize = 19;
pub const ENET0_TIMER: usize = 20;
pub const ENET_TXCLK: usize = 21;
pub const FLEXCAN1_RX: usize = 22;
pub const FLEXCAN2_RX: usize = 23;
pub const FLEXPWM1_PWMA3: usize = 24;
pub const FLEXPWM1_PWMA0: usize = 25;
pub const FLEXPWM1_PWMA1: usize = 26;
pub const FLEXPWM1_PWMA2: usize = 27;
pub const FLEXPWM1_PWMB3: usize = 28;
pub const FLEXPWM1_PWMB0: usize = 29;
pub const FLEXPWM1_PWMB1: usize = 30;
pub const FLEXPWM1_PWMB2: usize = 31;
pub const FLEXPWM2_PWMA3: usize = 32;
pub const FLEXPWM2_PWMA0: usize = 33;
pub const FLEXPWM2_PWMA1: usize = 34;
pub const FLEXPWM2_PWMA2: usize = 35;
pub const FLEXPWM2_PWMB3: usize = 36;
pub const FLEXPWM2_PWMB0: usize = 37;
pub const FLEXPWM2_PWMB1: usize = 38;
pub const FLEXPWM2_PWMB2: usize = 39;
pub const FLEXPWM4_PWMA0: usize = 40;
pub const FLEXPWM4_PWMA1: usize = 41;
pub const FLEXPWM4_PWMA2: usize = 42;
pub const FLEXPWM4_PWMA3: usize = 43;
pub const FLEXSPIA_DQS: usize = 44;
pub const FLEXSPIA_DATA0: usize = 45;
pub const FLEXSPIA_DATA1: usize = 46;
pub const FLEXSPIA_DATA2: usize = 47;
pub const FLEXSPIA_DATA3: usize = 48;
pub const FLEXSPIB_DATA0: usize = 49;
pub const FLEXSPIB_DATA1: usize = 50;
pub const FLEXSPIB_DATA2: usize = 51;
pub const FLEXSPIB_DATA3: usize = 52;
pub const FLEXSPIA_SCK: usize = 53;
pub const LPI2C1_SCL: usize = 54;
pub const LPI2C1_SDA: usize = 55;
pub const LPI2C2_SCL: usize = 56;
pub const LPI2C2_SDA: usize = 57;
pub const LPI2C3_SCL: usize = 58;
pub const LPI2C3_SDA: usize = 59;
pub const LPI2C4_SCL: usize = 60;
pub const LPI2C4_SDA: usize = 61;
pub const LPSPI1_PCS0: usize = 62;
pub const LPSPI1_SCK: usize = 63;
pub const LPSPI1_SDI: usize = 64;
pub const LPSPI1_SDO: usize = 65;
pub const LPSPI2_PCS0: usize = 66;
pub const LPSPI2_SCK: usize = 67;
pub const LPSPI2_SDI: usize = 68;
pub const LPSPI2_SDO: usize = 69;
pub const LPSPI3_PCS0: usize = 74;
pub const LPSPI3_SCK: usize = 75;
pub const LPSPI3_SDI: usize = 76;
pub const LPSPI3_SDO: usize = 77;
pub const LPUART2_RX: usize = 78;
pub const LPUART2_TX: usize = 79;
pub const LPUART3_CTS_B: usize = 80;
pub const LPUART3_RX: usize = 81;
pub const LPUART3_TX: usize = 82;
pub const LPUART4_RX: usize = 83;
pub const LPUART4_TX: usize = 84;
pub const LPUART5_RX: usize = 85;
pub const LPUART5_TX: usize = 86;
pub const LPUART6_RX: usize = 87;
pub const LPUART6_TX: usize = 88;
pub const LPUART7_RX: usize = 89;
pub const LPUART7_TX: usize = 90;
pub const LPUART8_RX: usize = 91;
pub const LPUART8_TX: usize = 92;
pub const NMI: usize = 93;
pub const QTIMER2_TIMER0: usize = 94;
pub const QTIMER2_TIMER1: usize = 95;
pub const QTIMER2_TIMER2: usize = 96;
pub const QTIMER2_TIMER3: usize = 97;
pub const QTIMER3_TIMER0: usize = 98;
pub const QTIMER3_TIMER1: usize = 99;
pub const QTIMER3_TIMER2: usize = 100;
pub const QTIMER3_TIMER3: usize = 101;
pub const SAI1_MCLK2: usize = 102;
pub const SAI1_RX_BCLK: usize = 103;
pub const SAI1_RX_DATA0: usize = 104;
pub const SAI1_RX_DATA1: usize = 105;
pub const SAI1_RX_DATA2: usize = 106;
pub const SAI1_RX_DATA3: usize = 107;
pub const SAI1_RX_SYNC: usize = 108;
pub const SAI1_TX_BCLK: usize = 109;
pub const SAI1_TX_SYNC: usize = 110;
pub const SAI2_MCLK2: usize = 111;
pub const SAI2_RX_BCLK: usize = 112;
pub const SAI2_RX_DATA0: usize = 113;
pub const SAI2_RX_SYNC: usize = 114;
pub const SAI2_TX_BCLK: usize = 115;
pub const SAI2_TX_SYNC: usize = 116;
pub const SPDIF_IN: usize = 117;
pub const USB_OTG1_OC: usize = 119;
pub const USDHC1_CD_B: usize = 120;
pub const USDHC1_WP: usize = 121;
pub const USDHC2_CLK: usize = 122;
pub const USDHC2_CD_B: usize = 123;
pub const USDHC2_CMD: usize = 124;
pub const USDHC2_DATA0: usize = 125;
pub const USDHC2_DATA1: usize = 126;
pub const USDHC2_DATA2: usize = 127;
pub const USDHC2_DATA3: usize = 128;
pub const USDHC2_DATA4: usize = 129;
pub const USDHC2_DATA5: usize = 130;
pub const USDHC2_DATA6: usize = 131;
pub const USDHC2_DATA7: usize = 132;
pub const USDHC2_WP: usize = 133;
pub const XBAR1_IN02: usize = 134;
pub const XBAR1_IN03: usize = 135;
pub const XBAR1_IN04: usize = 136;
pub const XBAR1_IN05: usize = 137;
pub const XBAR1_IN06: usize = 138;
pub const XBAR1_IN07: usize = 139;
pub const XBAR1_IN08: usize = 140;
pub const XBAR1_IN09: usize = 141;
pub const XBAR1_IN17: usize = 142;
pub const XBAR1_IN18: usize = 143;
pub const XBAR1_IN20: usize = 144;
pub const XBAR1_IN22: usize = 145;
pub const XBAR1_IN23: usize = 146;
pub const XBAR1_IN24: usize = 147;
pub const XBAR1_IN14: usize = 148;
pub const XBAR1_IN15: usize = 149;
pub const XBAR1_IN16: usize = 150;
pub const XBAR1_IN25: usize = 151;
pub const XBAR1_IN19: usize = 152;
pub const XBAR1_IN21: usize = 153;
pub const FLEXSPI2_IPP_IND_DQS_FA: usize = 206;
pub const FLEXSPI2_IPP_IND_IO_FA_BIT0: usize = 207;
pub const FLEXSPI2_IPP_IND_IO_FA_BIT1: usize = 208;
pub const FLEXSPI2_IPP_IND_IO_FA_BIT2: usize = 209;
pub const FLEXSPI2_IPP_IND_IO_FA_BIT3: usize = 210;
pub const FLEXSPI2_IPP_IND_IO_FB_BIT0: usize = 211;
pub const FLEXSPI2_IPP_IND_IO_FB_BIT1: usize = 212;
pub const FLEXSPI2_IPP_IND_IO_FB_BIT2: usize = 213;
pub const FLEXSPI2_IPP_IND_IO_FB_BIT3: usize = 214;
pub const FLEXSPI2_IPP_IND_SCK_FA: usize = 215;
pub const FLEXSPI2_IPP_IND_SCK_FB: usize = 216;
pub const GPT1_IPP_IND_CAPIN1: usize = 217;
pub const GPT1_IPP_IND_CAPIN2: usize = 218;
pub const GPT1_IPP_IND_CLKIN: usize = 219;
pub const GPT2_IPP_IND_CAPIN1: usize = 220;
pub const GPT2_IPP_IND_CAPIN2: usize = 221;
pub const GPT2_IPP_IND_CLKIN: usize = 222;
pub const SAI3_IPG_CLK_SAI_MCLK_S: usize = 223;
pub const SAI3_IPP_IND_SAI_RXBCLK: usize = 224;
pub const SAI3_IPP_IND_SAI_RXDATA_S: usize = 225;
pub const SAI3_IPP_IND_SAI_RXSYNC: usize = 226;
pub const SAI3_IPP_IND_SAI_TXBCLK: usize = 227;
pub const SAI3_IPP_IND_SAI_TXSYNC: usize = 228;
pub const SEMC_I_IPP_IND_DQS4: usize = 229;
pub const CANFD_IPP_IND_CANRX: usize = 230;
}
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