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#[repr(C)]
#[allow(non_snake_case)]
pub struct RegisterBlock {
pub CONTROL: u32,
pub CONTROL_SET: u32,
pub CONTROL_CLR: u32,
pub CONTROL_TOG: u32,
_reserved0: [u8; 16],
pub STATUS0: u32,
_reserved1: [u8; 12],
pub AUTHEN: u32,
_reserved2: [u8; 76],
}
ral_registers::register! {
#[doc = "Clock Root Control Register"]
pub CONTROL<u32> RW [
#[doc = "Clock division fraction."]
DIV start(0) width(8) RW {}
#[doc = "Clock multiplexer."]
MUX start(8) width(2) RW {}
#[doc = "Shutdown clock root."]
OFF start(24) width(1) RW {}
]
}
pub use CONTROL as CONTROL_SET;
pub use CONTROL as CONTROL_CLR;
pub use CONTROL as CONTROL_TOG;
ral_registers::register! {
#[doc = "Clock root working status"]
pub STATUS0<u32> RO [
#[doc = "Current clock root DIV setting"]
DIV start(0) width(8) RO {}
#[doc = "Current clock root MUX setting"]
MUX start(8) width(2) RO {}
#[doc = "Current clock root OFF setting"]
OFF start(24) width(1) RO {}
#[doc = "Internal updating in generation logic Indication for clock generation logic is applying new setting."]
SLICE_BUSY start(28) width(1) RO {}
#[doc = "Indication for clock root internal logic is updating. This status is a combination of UPDATE_FORWARD and SLICE_BUSY."]
CHANGING start(31) width(1) RO {}
]
}
ral_registers::register! {
#[doc = "Clock root access control"]
pub AUTHEN<u32> RW [
#[doc = "User access permission"]
TZ_USER start(8) width(1) RW {}
#[doc = "Non-secure access permission"]
TZ_NS start(9) width(1) RW {}
#[doc = "Lock TrustZone settings"]
LOCK_TZ start(11) width(1) RW {}
#[doc = "Lock white list"]
LOCK_LIST start(15) width(1) RW {}
#[doc = "Whitelist settings"]
WHITE_LIST start(16) width(16) RW {}
]
}
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