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#![no_std]
pub mod iomuxc_gpr {
#[repr(C)]
#[allow(non_snake_case)]
pub struct RegisterBlock<const GPR_REGISTERS: usize> {
pub GPR: [u32; GPR_REGISTERS],
}
ral_registers::register!(pub GPR<u32> RW []);
}
pub mod iomuxc {
#[repr(C)]
#[allow(non_snake_case)]
pub struct RegisterBlock<
const OFFSET_BYTES: usize,
const PAD_REGISTERS: usize,
const SELECT_INPUT: usize,
> {
_reserved: [u8; OFFSET_BYTES],
pub SW_MUX_CTL_PAD: [u32; PAD_REGISTERS],
pub SW_PAD_CTL_PAD: [u32; PAD_REGISTERS],
pub SELECT_INPUT: [u32; SELECT_INPUT],
}
ral_registers::register! {
/// Multiplex control register.
pub SW_MUX_CTL_PAD<u32> RW [
/// Multiplex selection.
///
/// Note that this bitwidth may be larger than
/// what is implemented for your IP. Consult
/// your part's reference manual for more information.
MUX_MODE start(0) width(4) RW {}
/// Software Input On.
SION start(4) width(1) RW {}
]}
ral_registers::register! {
/// Pad control register.
pub SW_PAD_CTL_PAD<u32> RW [
/// Slew rate.
SRE start(0) width(1) RW {
/// Slow slew rate.
SLOW = 0,
/// Fast slew rate.
FAST = 1,
}
/// Drive strength.
DSE start(3) width(3) RW {
DISABLED = 0,
R0 = 1,
R0_2 = 2,
R0_3 = 3,
R0_4 = 4,
R0_5 = 5,
R0_6 = 6,
R0_7 = 7,
}
/// Speed.
SPEED start(6) width(2) RW {
LOW_50MHZ = 0,
MEDIUM_100MHz = 1,
FAST_150MHZ = 2,
MAX_200MHZ = 3,
}
/// Open drain enable.
ODE start(11) width(1) RW {}
/// Pull / keep enable.
PKE start(12) width(1) RW {}
/// Pull / keep select
PUE start(13) width(1) RW {
/// Use the keeper.
KEEPER = 0,
/// Use the PU / PD.
PULL = 1,
}
/// Pull up / down selection.
PUS start(14) width(2) RW {
/// 100K Ohm Pull Down
PD_100K_OHM = 0,
/// 47K Ohm Pull Up
PU_47K_OHM = 0x01,
/// 100K Ohm Pull Up
PU_100K_OHM = 0x02,
/// 22K Ohm Pull Up
PU_22K_OHM = 0x03,
}
/// Hysteresis enable.
HYS start(16) width(1) RW {}
]
}
ral_registers::register! {
pub SELECT_INPUT<u32> RW []
}
}
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