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#![no_std]
pub type Instance = ral_registers::Instance<RegisterBlock>;
#[repr(C)]
#[allow(non_snake_case)]
pub struct RegisterBlock {
reserved_0: [u8; 1280],
pub PMU_LDO_PLL: u32,
reserved_1: [u8; 76],
pub PMU_BIAS_CTRL: u32,
reserved_2: [u8; 12],
pub PMU_BIAS_CTRL2: u32,
reserved_3: [u8; 12],
pub PMU_REF_CTRL: u32,
reserved_4: [u8; 12],
pub PMU_POWER_DETECT_CTRL: u32,
reserved_5: [u8; 124],
pub LDO_PLL_ENABLE_SP: u32,
reserved_6: [u8; 12],
pub LDO_LPSR_ANA_ENABLE_SP: u32,
reserved_7: [u8; 12],
pub LDO_LPSR_ANA_LP_MODE_SP: u32,
reserved_8: [u8; 12],
pub LDO_LPSR_ANA_TRACKING_EN_SP: u32,
reserved_9: [u8; 12],
pub LDO_LPSR_ANA_BYPASS_EN_SP: u32,
reserved_10: [u8; 12],
pub LDO_LPSR_ANA_STBY_EN_SP: u32,
reserved_11: [u8; 12],
pub LDO_LPSR_DIG_ENABLE_SP: u32,
reserved_12: [u8; 12],
pub LDO_LPSR_DIG_TRG_SP0: u32,
reserved_13: [u8; 12],
pub LDO_LPSR_DIG_TRG_SP1: u32,
reserved_14: [u8; 12],
pub LDO_LPSR_DIG_TRG_SP2: u32,
reserved_15: [u8; 12],
pub LDO_LPSR_DIG_TRG_SP3: u32,
reserved_16: [u8; 12],
pub LDO_LPSR_DIG_LP_MODE_SP: u32,
reserved_17: [u8; 12],
pub LDO_LPSR_DIG_TRACKING_EN_SP: u32,
reserved_18: [u8; 12],
pub LDO_LPSR_DIG_BYPASS_EN_SP: u32,
reserved_19: [u8; 12],
pub LDO_LPSR_DIG_STBY_EN_SP: u32,
reserved_20: [u8; 12],
pub BANDGAP_ENABLE_SP: u32,
reserved_21: [u8; 28],
pub RBB_SOC_ENABLE_SP: u32,
reserved_22: [u8; 12],
pub RBB_LPSR_ENABLE_SP: u32,
reserved_23: [u8; 12],
pub BANDGAP_STBY_EN_SP: u32,
reserved_24: [u8; 12],
pub PLL_LDO_STBY_EN_SP: u32,
reserved_25: [u8; 28],
pub RBB_SOC_STBY_EN_SP: u32,
reserved_26: [u8; 12],
pub RBB_LPSR_STBY_EN_SP: u32,
reserved_27: [u8; 28],
pub RBB_LPSR_CONFIGURE: u32,
reserved_28: [u8; 12],
pub RBB_SOC_CONFIGURE: u32,
reserved_29: [u8; 12],
pub REFTOP_OTP_TRIM_VALUE: u32,
reserved_30: [u8; 28],
pub LPSR_1P8_LDO_OTP_TRIM_VALUE: u32,
}
ral_registers::register! {
#[doc = "PMU_LDO_PLL_REGISTER"]
pub PMU_LDO_PLL<u32> RW [
#[doc = "LDO_PLL_ENABLE"]
LDO_PLL_ENABLE start(0) width(1) RW {}
#[doc = "LDO_PLL_CONTROL_MODE"]
LDO_PLL_CONTROL_MODE start(1) width(1) RW {
#[doc = "SW Control"]
SOFTWARE = 0,
#[doc = "HW Control"]
HARDWARE = 0x1,
}
#[doc = "ldo_pll_ai_toggle"]
LDO_PLL_AI_TOGGLE start(16) width(1) RW {}
#[doc = "ldo_pll_busy"]
LDO_PLL_AI_BUSY start(30) width(1) RO {}
]
}
ral_registers::register! {
#[doc = "LDO_PLL_ENABLE_SP_REGISTER"]
pub LDO_PLL_ENABLE_SP<u32> RW []
}
ral_registers::register! {
#[doc = "PMU_REF_CTRL_REGISTER"]
pub PMU_REF_CTRL<u32> RW [
#[doc = "ref_ai_toggle"]
REF_AI_TOGGLE start(0) width(1) RW {}
#[doc = "ref_ai_busy"]
REF_AI_BUSY start(1) width(1) RO {}
#[doc = "REF_ENABLE"]
REF_ENABLE start(2) width(1) RW {}
#[doc = "REF_CONTROL_MODE"]
REF_CONTROL_MODE start(3) width(1) RW {
#[doc = "SW Control"]
SOFTWRE = 0,
#[doc = "HW Control"]
HARDWARE = 0x1,
}
#[doc = "en_pll_vol_ref_buffer"]
EN_PLL_VOL_REF_BUFFER start(4) width(1) RW {}
]
}
/// Specify which setpoints enable the PHY LDO.
///
/// A high bit in `setpoints` signals "enable."
pub fn set_phy_ldo_setpoints(pmu: Instance, setpoints: u16) {
// Logic is inverted in hardware.
let setpoints: u16 = !setpoints;
ral_registers::write_reg!(self, pmu, LDO_PLL_ENABLE_SP, setpoints as u32);
}
/// Manage the PHY LDO with setpoints.
pub fn enable_phy_ldo_setpoints(pmu: Instance) {
ral_registers::modify_reg!(self, pmu, PMU_LDO_PLL, LDO_PLL_CONTROL_MODE: HARDWARE);
}
/// Manage the PLL reference with setpoints.
pub fn enable_pll_reference_setpoints(pmu: Instance) {
ral_registers::modify_reg!(self, pmu, PMU_REF_CTRL, REF_CONTROL_MODE: HARDWARE);
}
/// Enable or disable the PLL bandgap reference voltage.
pub fn enable_pll_reference_voltage(pmu: Instance, enable: bool) {
ral_registers::modify_reg!(self, pmu, PMU_REF_CTRL, EN_PLL_VOL_REF_BUFFER: enable as u32);
}
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