diff options
| author | Ian McIntyre <me@mciantyre.dev> | 2026-02-01 11:09:48 -0500 |
|---|---|---|
| committer | Ian McIntyre <me@mciantyre.dev> | 2026-02-01 11:33:03 -0500 |
| commit | 86978556cfd7fd1f82252c1bee19a6a1f1957b08 (patch) | |
| tree | 77be38e0f4025ed7e953d2f9b08b0e64e7628bd3 /imxrt1040 | |
| parent | 135dc4fce370711e51ec6d839fb400e0cda955f9 (diff) | |
Add 1040evk target-gen test
Diffstat (limited to 'imxrt1040')
| -rw-r--r-- | imxrt1040/src/lib.rs | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/imxrt1040/src/lib.rs b/imxrt1040/src/lib.rs index c5237c9..66857b7 100644 --- a/imxrt1040/src/lib.rs +++ b/imxrt1040/src/lib.rs @@ -4,7 +4,8 @@ use core::num::NonZero; pub use imxrt_flash_algos::*; -use imxrt1040::{ccm, dcdc, instances}; +use imxrt1040::{ccm, dcdc, instances, iomuxc}; +use ral_registers as ral; const AHB_CONFIG: ccm::AbhConfiguration = ccm::AbhConfiguration { div_sel: 100, @@ -42,9 +43,32 @@ impl imxrt10xx::Imxrt10xx for Imxrt1040 { const FLEXSPI_FIFO_CAPACITY_BYTES: usize = 128; + type IOMUXC = imxrt1040::iomuxc::Instance; + const IOMUXC_INSTANCE: Self::IOMUXC = unsafe { instances::iomuxc() }; + fn configure_clocks(ccm: ccm::CCM, ccm_analog: ccm::CCM_ANALOG, dcdc: dcdc::Instance) { self::configure_clocks(ccm, ccm_analog, dcdc); } + + fn configure_pins(iomuxc: Self::IOMUXC) { + use iomuxc::pad; + + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_05], MUX_MODE: 1, SION: 1); // DQS + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_06], MUX_MODE: 1, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_07], MUX_MODE: 1, SION: 1); // SCK + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_08], MUX_MODE: 1, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_09], MUX_MODE: 1, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_10], MUX_MODE: 1, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_11], MUX_MODE: 1, SION: 0); + + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_05], PUE: 1, PKE: 1, SPEED: MEDIUM_100MHZ, DSE: R0, PUS: PD_100K_OHM); // DQS + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_06], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_07], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_08], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_09], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_10], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_11], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + } } pub type Algorithm<const FLASH_SIZE_BYTES: usize> = |