diff options
| author | Ian McIntyre <me@mciantyre.dev> | 2025-12-17 19:33:41 -0500 |
|---|---|---|
| committer | Ian McIntyre <me@mciantyre.dev> | 2025-12-17 21:28:52 -0500 |
| commit | fa5b0daeb02bb1775462ac57b353589d983fa2bb (patch) | |
| tree | ef71ac3c591a103df61dfe5c75c911065387d662 /src | |
| parent | 53f0e5d382b346aa8b8c5cf221fa3b2464ef4617 (diff) | |
Diffstat (limited to 'src')
| -rw-r--r-- | src/imxrt11xx.rs | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/imxrt11xx.rs b/src/imxrt11xx.rs index ed83668..0fc3ae1 100644 --- a/src/imxrt11xx.rs +++ b/src/imxrt11xx.rs @@ -3,11 +3,42 @@ use core::{marker::PhantomData, num::NonZero}; use imxrt_drivers_ccm_11xx::ral_11xx as ccm; use imxrt_drivers_flexspi as flexspi; use imxrt_drivers_gpc_11xx::cpu_mode_ctrl as gpc_cpu; +use imxrt_drivers_iomuxc_11xx::iomuxc; use imxrt_drivers_pmu_11xx as pmu; use imxrt_drivers_rtwdog as rtwdog; +use ral_registers as ral; + const FLEXSPI1_BASE: u32 = 0x3000_0000; +/// Assumes the boot ROM's primary FlexSPI1 interface. +fn configure_pins(iomuxc: iomuxc::Instance) { + use iomuxc::select_input::*; + + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD.GPIO_SD_B2[5], MUX_MODE: 1, SION: 1); // DQS + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD.GPIO_SD_B2[6], MUX_MODE: 1, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD.GPIO_SD_B2[7], MUX_MODE: 1, SION: 1); // SCK + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD.GPIO_SD_B2[8], MUX_MODE: 1, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD.GPIO_SD_B2[9], MUX_MODE: 1, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD.GPIO_SD_B2[10], 1); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD.GPIO_SD_B2[11], 1); + + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD.GPIO_SD_B2[5], PDRV: NORMAL, PULL: PULL_DOWN); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD.GPIO_SD_B2[6], PDRV: NORMAL, PULL: NO_PULL); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD.GPIO_SD_B2[7], PDRV: NORMAL, PULL: NO_PULL); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD.GPIO_SD_B2[8], PDRV: NORMAL, PULL: NO_PULL); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD.GPIO_SD_B2[9], PDRV: NORMAL, PULL: NO_PULL); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD.GPIO_SD_B2[10], PDRV: NORMAL, PULL: NO_PULL); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD.GPIO_SD_B2[11], PDRV: NORMAL, PULL: NO_PULL); + + ral::write_reg!(iomuxc, iomuxc, SELECT_INPUT[FLEXSPI1_I_DQS_FA], 2); + ral::write_reg!(iomuxc, iomuxc, SELECT_INPUT[FLEXSPI1_I_IO_FA_0], 1); + ral::write_reg!(iomuxc, iomuxc, SELECT_INPUT[FLEXSPI1_I_IO_FA_1], 1); + ral::write_reg!(iomuxc, iomuxc, SELECT_INPUT[FLEXSPI1_I_IO_FA_2], 1); + ral::write_reg!(iomuxc, iomuxc, SELECT_INPUT[FLEXSPI1_I_IO_FA_3], 1); + ral::write_reg!(iomuxc, iomuxc, SELECT_INPUT[FLEXSPI1_I_SCK_FA], 1); +} + /// Establish the core, bus, and FlexSPI /// clock frequencies. fn configure_clocks( @@ -121,6 +152,7 @@ pub trait Imxrt11xx: 'static { const CCM_PLL_INSTANCE: ccm::pll::Instance; const GPC_CPU_INSTANCE: gpc_cpu::Instance; const RTWDOG_INSTANCE: rtwdog::Instance; + const IOMUXC_INSTANCE: iomuxc::Instance; const FLEXSPI_FIFO_CAPACITY_BYTES: usize; } @@ -143,6 +175,7 @@ impl<C: Imxrt11xx, F: crate::ImxrtFlashAlgorithm> Algorithm<C, F> { pub fn initialize() -> Self { rtwdog::disable(C::RTWDOG_INSTANCE); + configure_pins(C::IOMUXC_INSTANCE); configure_clocks( C::CCM_INSTANCE, C::CCM_PLL_INSTANCE, |