diff options
Diffstat (limited to 'imxrt1010/src')
| -rw-r--r-- | imxrt1010/src/lib.rs | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/imxrt1010/src/lib.rs b/imxrt1010/src/lib.rs index 873dd58..606556a 100644 --- a/imxrt1010/src/lib.rs +++ b/imxrt1010/src/lib.rs @@ -45,14 +45,14 @@ impl imxrt10xx::Imxrt10xx for Imxrt1010 { ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_08], MUX_MODE: 0, SION: 0); ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_11], MUX_MODE: 0, SION: 0); - ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_12], PUE: 1, PKE: 1, SPEED: MEDIUM_100MHZ, DSE: R0, PUS: PD_100K_OHM); // DQS - ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_06], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); - ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_05], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); - ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_10], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); - ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_09], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); - ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_07], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); - ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_08], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); - ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_11], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_12], PUE: 1, PKE: 1, SPEED: MAX_200MHZ, DSE: R0_6, PUS: PD_100K_OHM); // DQS + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_06], PUE: 0, PKE: 1, SPEED: MAX_200MHZ, DSE: R0_6); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_05], PUE: 0, PKE: 1, SPEED: MAX_200MHZ, DSE: R0_6); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_10], PUE: 0, PKE: 1, SPEED: MAX_200MHZ, DSE: R0_6); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_09], PUE: 0, PKE: 1, SPEED: MAX_200MHZ, DSE: R0_6); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_07], PUE: 0, PKE: 1, SPEED: MAX_200MHZ, DSE: R0_6); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_08], PUE: 0, PKE: 1, SPEED: MAX_200MHZ, DSE: R0_6); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_11], PUE: 0, PKE: 1, SPEED: MAX_200MHZ, DSE: R0_6); ral::write_reg!( iomuxc, |