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//! Interface package for writing flash algorithms for 1040 MCUs.
#![no_std]
use core::num::NonZero;
pub use imxrt_flash_algos::*;
use imxrt1040::{ccm, dcdc, instances, iomuxc};
use ral_registers as ral;
const AHB_CONFIG: ccm::AbhConfiguration = ccm::AbhConfiguration {
div_sel: 100,
arm_divider: 2,
ahb_divider: 1,
};
const _: () = assert!(AHB_CONFIG.ahb_frequency() == 600_000_000);
fn configure_clocks(ccm: ccm::CCM, ccm_analog: ccm::CCM_ANALOG, dcdc: dcdc::Instance) {
dcdc::set_target_vdd_soc(dcdc, 1250);
ccm::configure_ahb(ccm, ccm_analog, &AHB_CONFIG);
ccm::clock_gate::set(ccm, ccm::gates::FLEXSPI1, false.into());
ccm::pll2::restart(ccm_analog);
ral_registers::modify_reg!(ccm::ral::ccm_analog, ccm_analog, PFD_528, PFD2_FRAC: PFD2_FRAC.get());
ccm::flexspi1_clk::set_divider(ccm, 3);
ccm::flexspi1_clk::set_selection(ccm, ccm::flexspi1_clk::Selection::Pll2Pfd2);
ccm::clock_gate::set(ccm, ccm::gates::FLEXSPI1, true.into());
}
const PFD2_FRAC: NonZero<u32> = ccm::pll2::pll_pfd_divider(396_000_000).unwrap();
pub struct Imxrt1040;
impl imxrt10xx::Imxrt10xx for Imxrt1040 {
const FLEXSPI1_INSTANCE: imxrt1040::flexspi::Instance = unsafe { instances::flexspi1() };
const CCM_INSTANCE: ccm::CCM = unsafe { instances::ccm() };
const CCM_ANALOG_INSTANCE: ccm::CCM_ANALOG = unsafe { instances::ccm_analog() };
const DCDC_INSTANCE: dcdc::Instance = unsafe { instances::dcdc() };
const FLEXSPI_FIFO_CAPACITY_BYTES: usize = 128;
type IOMUXC = imxrt1040::iomuxc::Instance;
const IOMUXC_INSTANCE: Self::IOMUXC = unsafe { instances::iomuxc() };
fn configure_clocks(ccm: ccm::CCM, ccm_analog: ccm::CCM_ANALOG, dcdc: dcdc::Instance) {
self::configure_clocks(ccm, ccm_analog, dcdc);
}
fn configure_pins(iomuxc: Self::IOMUXC) {
use iomuxc::pad;
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_05], MUX_MODE: 1, SION: 1); // DQS
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_06], MUX_MODE: 1, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_07], MUX_MODE: 1, SION: 1); // SCK
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_08], MUX_MODE: 1, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_09], MUX_MODE: 1, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_10], MUX_MODE: 1, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_B1_11], MUX_MODE: 1, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_05], PUE: 1, PKE: 1, SPEED: MEDIUM_100MHZ, DSE: R0, PUS: PD_100K_OHM); // DQS
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_06], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_07], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_08], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_09], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_10], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_B1_11], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
}
}
pub type Algorithm<const FLASH_SIZE_BYTES: usize> =
imxrt10xx::Algorithm<Imxrt1040, FLASH_SIZE_BYTES>;
|
