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authorIan McIntyre <me@mciantyre.dev>2025-02-22 13:04:40 -0500
committerIan McIntyre <me@mciantyre.dev>2025-02-22 13:04:40 -0500
commit81b2043a235375a31468d562cea2a301d2bb9449 (patch)
treed03063b05140fe3f5950786dbff65eacd63c2ec4 /examples
parent9aa3f9434740dc7552cfe86e8c33cbf5d6affca4 (diff)
Document workaround for registering exceptions
Given the way this package abuses cortex-m-rt, it's not immediately obvious how to register a Cortex-M exception handler with the `#[exception]` macro. This commit documents and demonstrates the workaround I use.
Diffstat (limited to 'examples')
-rw-r--r--examples/blink-blocking.rs24
1 files changed, 23 insertions, 1 deletions
diff --git a/examples/blink-blocking.rs b/examples/blink-blocking.rs
index a3a71b9..1ae62b4 100644
--- a/examples/blink-blocking.rs
+++ b/examples/blink-blocking.rs
@@ -1,7 +1,10 @@
//! Slowly blink an LED while blocking on a timer.
//!
//! Use this as the minimum-viable runtime support. You don't
-//! need interrupts for this example.
+//! need MCU-specific interrupts for this example.
+//!
+//! This example demonstrates how to register an exception
+//! handler. See the API documentation for more information.
#![no_std]
#![no_main]
@@ -16,3 +19,22 @@ fn main() -> ! {
pit.blocking_delay();
}
}
+
+use imxrt_rt::exception;
+
+#[exception]
+unsafe fn DefaultHandler(_irqn: i16) {
+ uh_oh()
+}
+
+#[exception]
+unsafe fn HardFault(_: &imxrt_rt::ExceptionFrame) -> ! {
+ uh_oh()
+}
+
+#[inline(never)]
+fn uh_oh() -> ! {
+ loop {
+ core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst)
+ }
+}