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| author | Adam Greig <adam@adamgreig.com> | 2023-01-03 17:38:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-03 17:38:58 +0000 |
| commit | 1b5e99297f6303fc20da2622ae815b3a4987dbb1 (patch) | |
| tree | dacbb6bb70d8ba62a616d8df693503c799a1575d /CHANGELOG.md | |
| parent | c3a5ddfdb8e2d9995436a0c4e76ca04b48e4603d (diff) | |
| parent | 83e35f81ff4f69e04dbea12c03a853f2939f262b (diff) | |
Merge pull request #6 from adamgreig/0.1.2
Release 0.1.2
Diffstat (limited to 'CHANGELOG.md')
| -rw-r--r-- | CHANGELOG.md | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index 0bd0d85..7a29e26 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,10 @@ ## [Unreleased] +## [v0.1.2] - 2023-01-03 + +* Support register-array access (#5) + ## [v0.1.1] - 2021-09-29 * Mark all registers as `#[repr(transparent)]` (#1) @@ -11,6 +15,7 @@ * Initial release. Registers and macros imported from `stm32ral` project. -[Unreleased]: https://github.com/adamgreig/ral-registers/compare/v0.1.1...HEAD +[Unreleased]: https://github.com/adamgreig/ral-registers/compare/v0.1.2...HEAD +[v0.1.2]: https://github.com/adamgreig/ral-registers/tree/v0.1.2 [v0.1.1]: https://github.com/adamgreig/ral-registers/tree/v0.1.1 [v0.1.0]: https://github.com/adamgreig/ral-registers/tree/v0.1.0 |