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authorRomán Cárdenas Rodríguez <rcardenas.rod@gmail.com>2025-02-18 09:39:38 +0100
committerHenrik Tjäder <henrik@tjaders.com>2025-03-12 19:41:40 +0000
commit5d5ecb95c2dc52b414f5a2aeb3fa77b4089b6320 (patch)
treef5f7bd7d7ba6a309226d389c649a6bd88f1eeda7 /README.md
parent4542367fc9f2683afa5cd02df7322654aef5eb10 (diff)
Adding docs about RISC-V
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@@ -41,6 +41,9 @@ A concurrency framework for building real-time systems.
- **All Cortex-M devices are fully supported**.
+- **Most RISC-V devices are supported**. Refer to the [RTIC book]((https://rtic.rs/))
+ to learn more about RISC-V backends, their particularities, and their limitations.
+
- This task model is amenable to known WCET (Worst Case Execution Time) analysis
and scheduling analysis techniques.