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| author | shueja <32416547+shueja@users.noreply.github.com> | 2025-10-08 19:45:09 -0700 |
|---|---|---|
| committer | Henrik TjΓ€der <henrik@tjaders.com> | 2025-10-09 07:53:15 +0200 |
| commit | 181e667da3cecaca1c3ee3a897c0b66b288cd675 (patch) | |
| tree | 57323a7c7d8fb81e49d1e8e297563eb089ad7b6e /book/en/src | |
| parent | 300ad99b74b7d1f4e81633344ef7f68cb3dfbced (diff) | |
Fix algorithm typo in preface.md
Diffstat (limited to 'book/en/src')
| -rw-r--r-- | book/en/src/preface.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/book/en/src/preface.md b/book/en/src/preface.md index cb6901e..f08da91 100644 --- a/book/en/src/preface.md +++ b/book/en/src/preface.md @@ -125,7 +125,7 @@ For the running example, a snapshot of the ARM Cortex M [Nested Vectored Interru A claim (lock(r)) will change the current system ceiling (π«) and can be implemented as a *named* critical section: - old_ceiling = π«, π« = π
(r) - execute code within critical section - - old_ceiling = π« + - π« = old_ceiling This amounts to a resource protection mechanism, requiring only two machine instructions on enter and one on exit the critical section, for managing the `BASEPRI` register. For architectures lacking `BASEPRI`, we can implement the system ceiling through a set of machine instructions for disabling/enabling interrupts on entry/exit for the named critical section. The number of machine instructions vary depending on the number of mask registers that needs to be updated (a single machine operation can operate on up to 32 interrupts, so for the M0/M0+ architecture a single instruction suffice). RTIC will determine the ceiling values and masking constants at compile time, thus all operations is in Rust terms zero-cost. |