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| author | Eli Hastings <eli@seagen.io> | 2025-03-24 10:07:55 +0000 |
|---|---|---|
| committer | Henrik Tjäder <henrik@tjaders.com> | 2025-04-07 21:11:21 +0000 |
| commit | a032fa67b0f97b73b7cbbef038016af841f7d482 (patch) | |
| tree | 034d8c897a339d2dc4a0574604deb7effeb943dd /book/en/src | |
| parent | 104ee94dd1d0944ddcb29ac7c8b1634a659cb727 (diff) | |
Add ESP32C6 mention to book
Diffstat (limited to 'book/en/src')
| -rw-r--r-- | book/en/src/starting_a_project.md | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/book/en/src/starting_a_project.md b/book/en/src/starting_a_project.md index 915ff31..3c46961 100644 --- a/book/en/src/starting_a_project.md +++ b/book/en/src/starting_a_project.md @@ -21,6 +21,9 @@ To tackle this issue, currently, RTIC implements three different backends: - **`riscv-esp32c3-backend`**: This backend provides support for the ESP32-C3 SoC. In these devices, RTIC is very similar to its Cortex-M counterpart. +- **`riscv-esp32c6-backend`**: This backend provides support for the ESP32-C6 SoC. + In these devices, RTIC is very similar to its Cortex-M counterpart. + - **`riscv-mecall-backend`**: This backend provides support for **any** RISC-V device. In this backend, pending tasks trigger Machine Environment Call exceptions. The handler for this exception source dispatches pending tasks according to their priority. |